Accelerated Networking with SmartNICs in Azure
Explore the implementation of SmartNICs in Azure for accelerated networking, replacing the limitations of SR-IOV with programmable FPGAs. Discover the increasing NIC speed trends and the motivation behind utilizing programmable gate arrays for custom networking solutions in the public cloud.
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Presentation Transcript
Azure AcceleratedNetworking: SmartNICsin the PublicCloud CIS 800 lecture 3
Motivation Simple Version They have an existing system called VFP Virtual switch for Hyper-V / Azure Provides core SDN functionality for Azure networking services, including: Address Virtualization for VNET VIP -> DIP Translation for SLB ACLs, Metering, and Security Guards Uses programmable rule/flow tables to perform per- packet actions Programmed by multiple Azure SDN controllers, supports all dataplane policy at line rate with offloads
Motivation Simple Version Wanted to use Single Root IO Virtualization (SR-IOV) for performance But SR-IOV was a poor fit for what they needed Claims to be for virtualization, but doesn t allow composition Also relies on hardware vendors for new features
Solution Simple Version Let s just do it ourselves! Buy some programmable FPGAs (still cheaper than CPUs) Hire some hardware programmers (probably already have some)
What is an FPGA,Really? Field Programmable Gate Array Chip has large quantities of programmable gates highly parallel Program specialized circuits that communicate directly Two kinds of parallelism: Thread-level parallelism (stamp out multiple pipelines) Pipeline parallelism (create one long pipeline storing many packets at different stages) FPGA chips are now large SoCs (can run a control plane)
Solution Simple Version Let s just do it ourselves! Buy some programmable FPGAs (still cheaper than CPUs) Hire some hardware programmers (probably already have some) Straightforward solution Mirrors trends elsewhere in the datacenter Servers and Switches configurations are custom
Motivation More General NIC Speed, Gbps 2009: 1Gbps 2012: 10Gbps 2015: 40Gbps 2017: 50Gbps Soon: 100Gbps? 60 50 40 30 20 10 0 2009 2012 2015 2017 The network is getting faster, but CPU (at least single core) is not!
Siliconalternatives + Registers Control Unit (CU) + + CPUs G/NPUs ASICs Arithmetic Logic Unit (ALU) FPGAs + + + + FLEXIBILITY EFFICIENCY Moore s law means CPUs won t keep up with network speed
Siliconalternatives + Registers Control Unit (CU) + + CPUs G/NPUs ASICs Arithmetic Logic Unit (ALU) FPGAs + + + + FLEXIBILITY EFFICIENCY GPUs are great for bulk processing, but latency is not great
Siliconalternatives + Registers Control Unit (CU) + + CPUs G/NPUs ASICs Arithmetic Logic Unit (ALU) FPGAs + + + + FLEXIBILITY EFFICIENCY Slow to change Limited to exactly what the hardware vendor is willing to provide
Hardware or Bust SR-IOV is a classic example of an all or nothing offload its latency, jitter, CPU, performance benefits come from skipping the host entirely If even one widely-used action isn t supported in hardware, have to fall back to software path and most of the benefit is lost even if hardware can do 99% of the work Other examples: RDMA, DPDK, a common pattern This means we need to consider carefully how we will add new functionality to our hardware as needed over time How do we get the performance of hardware with programmability of software?
