Advanced Dual-Channel Time Domain Two-Step ADC Architecture
This detailed content explores the innovative design of a 12-bit 50 MS/s dual-channel time domain two-step ADC created by Tibi Galambos, Vladimir Koifman, and Anatoli Mordakhay of Analog Value Ltd. The architecture, sampling mechanism, layout, and algorithm of the ADC are thoroughly depicted, showcasing components like the voltage-to-time converter, sampling latches, clocking scheme, and current sources. Through insightful visuals and explanations, the content delves into the intricacies of the ADC's operation and design considerations for achieving high precision and efficiency.
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Presentation Transcript
A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC Tibi Galambos, Vladimir Koifman, Anatoli Mordakhay Analog Value Ltd. May 13, 2019 May 13, 2019 1
Overview ADC Architecture Sampling Voltage to Time Converter Sampling Latch Circuit ADC Layout Conclusions May 13, 2019 2
ADC Architecture Block Diagram dig_clk done Bubble Correct & Encode Bubble Correct & Encode Interpolator phi_start fine_start Phase Sampling Latches ph phi ref_clk Metastability Avoidance phi_end fine_end Oscillator PLL Counter Correction Multi-Phase Output Composing dout_i count_a_start Sampling Latches Counter A ca count_a_end dout_q count_b_start Sampling Latches Counter B cb count_b_end count_c_start Sampling Latches Counter C cc count_c_end Common pwm_in pwm_ip smp_clk vinip vinin Sampling V2T vinqp Channel i vinqn Channel q May 13, 2019 3 3
ADC Architecture Algorithm Case I Counter C contains number of cycles phi_start case I phi_end case II Fine bits phase difference Coarse bits counters Metastability avoidance Counter decrement phi_end case I phi_start case II Choose the counter that has the largest minimum absolute phase distance to the hit points. In this case C mindeltaph_c phi(nip) phi(0) Case II Counter C contains number of cycles + 1 May 13, 2019 4 4
Sampling Voltage to Time Converter - Schematics Input voltage sampled on C1 C2 generates a constant shift to help using the full dynamic range M1 acts as common source amplifier M2 acts as pre-charged comparator Idis is a switch-cap current source (see next slide) Sw7 F1 Cg Pwm_out Vdda_ref Sw1 Vdda_ref Vdda_ref Vin Vtop M2 F1 Idis Sw7 Sw3 F1 Sw4 F2 C1 Sw5 F1 Sw6 Vbot F2 C2 M1 Sw2 F1b May 13, 2019 5 5
Sampling Voltage to Time Converter Current Source The implementation uses the high frequency clocks from the PLL Given the use of the same type of capacitors for the current source and the integrating capacitor, ADC gain is process independent and only sensitive to matching Vdda_ref Vdda_ref Sw2 F1cs Sw4 F2cs C Sw3 F2cs Sw1 F1cs Vdda_ref R M3 Idis C R May 13, 2019 6 6
Sampling Voltage to Time Converter - Waveforms Input voltage sampled during F1 Linear Ramp and V2T conversion is done during F2 F1 F2 Vin Vi Vi+2 Vtop Vbot Vi+1 Vt_M2 Vt_M1 Pwm_out Ti Ti+2 Ti+1 May 13, 2019 7 7
Sampling Latch - Schematics M13 distributed voltage source M1, M2 measure the input voltage When comp_p is low, the regenerative feedback circuit is pre-charged On falling edge of comp_n the information is applied to the regenerative feedback (M9-M12) comp_p Vbias M14 M15 M13 M16 M17 R C M11 M12 out_p M1 M2 Vin_p Vin_n out_n M9 M10 M3 M4 comp_n M7 M8 M5 M6 May 13, 2019 8 8
ADC Test Chip and Layout May 13, 2019 9 9
Conclusion A novel 12 bit ADC was designed and fabricated in GF 22nm FDSOI technology Power consumption (for 2 channels) is 4 mW Silicon area 0.05 mm2 Measured an ENOB of 10.5 May 13, 2019 10
Thanks for your attention May 13, 2019 11 11
