Advanced FPGA Design: Ensuring Safety, Reliability, and Predictability
With a background in MSc Applied Physics and 10 years of experience in FPGA development, the focus is on verifying asynchronous and analog aspects of FPGA design for safe, reliable, and robust performance. Limited resources and articles drive the need to collaborate for knowledge sharing and exploring different CDC topologies and build tool settings. Connect on LinkedIn for insightful discussions.
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Presentation Transcript
34 a MSc Applied Physics 10 years FPGA development Entrepreneur Articles on Linkedin
40 minute sesh Please ask questions
... to verify? Asynchronous/analog aspect of FPGA design Behavior varies with FPGA individual Temperature Humidity Radiation etc... We want Safe, reliable, robust Predictable
... to google? Very few articles Limited scope A lot of bad advice out there
Because we rarely work on it How many hours per year?
Two heads are better than one GitHub, Linkedin, this talk 15k article views
hdl-modules.com github.com/hdl-modules/hdl-modules
hdl-modules.com github.com/hdl-modules/hdl-modules Articles on Linkedin Analysis of different CDC topologies Discussion about constraints Build tool settings And more... linkedin.com/in/lukas-vik
