Advanced IC Design for Precision Timing Applications

lucas timmermans n.w
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Explore cutting-edge IC designs for precision timing applications, enabling high performance in scientific research, CERN projects, and specific custom solutions. Learn about PICOPIX chips, clock signal generation, distributed clocks, Delay-Locked Loops (DLL), and more to meet stringent accuracy requirements.

  • IC design
  • Precision timing
  • PICOPIX chips
  • Clock signals
  • Scientific research

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  1. LUCAS TIMMERMANS IC DESIGN PICOPIX TIMING Nikhef 19-05-2025 ltimmers@nikhef.nl

  2. CHIPS IN RESEARCH Enables high precision in scientific research General ICs High performance general solutions Custom ICs: the cutting edge Very specific applications Wherecommercial solutions fall short 2 IC design picopix timing

  3. ICS AT CERN Nikhef chips for CERN Radiation High data rates Tight power constraints Timepix 3 Timepix 4 VELOpix 3 IC design picopix timing

  4. PICOPIX CHIP Technology: 28nm Area: 256x256 pixels Spatial resolution: <55um Timing: <25ps RMS Radiation hardness: <1Grad 4 IC design picopix timing

  5. PICOPIX TIMING Clock signal Generated from source on chip Accurate frequency and phase Used as reference for timing Clock distribution limits accuracy Accuracy needed of <5ps RMS 15mm 1/320MHz V 19.3mm t 5 IC design picopix timing

  6. PICOPIX TIMING Distributed clock Two pixels Different delays Vary with temperature and voltage Inaccuracy >5ps 15mm Pixel 2 V 19.3mm Pixel 1 t 6 IC design picopix timing

  7. PICOPIX TIMING: DLL DLL: Delay Locked Loop Accurate timing Power and temperature robust Low power and low area 7 IC design picopix timing

  8. PICOPIX TIMING: DLL Loop clock Add buffers 8 IC design picopix timing

  9. PICOPIX TIMING: DLL Half of total delay Same path up and down Half of the delay at the top Voltage and temperature changing total delay Measuring delay is not feasible Total delay Clock source 9 IC design picopix timing

  10. PICOPIX TIMING: DLL =1/8T Give each buffer a specific delay Makes the source and returning clock signals match Still subject to power and temperature v T in t v out t 10 IC design picopix timing

  11. PICOPIX TIMING: DLL Delay Locked Loop 11 IC design picopix timing

  12. PICOPIX DLL RESULTS No DLL RMS 200ps Results: Accuracy specifications are achieved Limitations: Input clock Static offset Supply noise DLL RMS 5ps 12 IC design picopix timing

  13. Results: Accuracy specifications are achieved Limitations: Input clock Static offset Supply noise 13 Presentatie titel

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