Advanced XOR Gate Implementations and Transistor Optimization

Lecture 2 Platform 0 revisited Computing platforms, semester 2 Novosibirsk State University University of Hertfordshire D. Irtegov, A.Shafarenko 2019

10.4 XOR-gate The XOR-gate has two inputs, A and B, and one output. The output terminal asserts the value A B, where is the logical connective exclusive or (also known as addition modulo 2) under the standard interpretation of signals. The truth table of an XOR-gate is as follows: XOR gate A 0 0 1 1 B 0 1 0 1 A xor B 0 1 1 0 4 NAND gates * 4 transistors each = 16 transistors Thereareseveral implementationsof theXOR-gatein Platform 0 Let usstart with themost straightforward one. Surprisingly this gate takes three times the number of transistors we needed for NAND/ NOR. The circuit is well structured and easy to understand. The two pairs of transistors at the bottom areconnected to form by now familiar NOT-gates, the intention being to produce inverse signals A0and B0so that we may use both the original A and B and their inverses. The top four transistors are P-type, pulling up to the power supply, i.e. 1. The output wire (A xor B) is at 1 when either the left pair or the right pair are open. The former happens when A = B0= 0, and the latter when B = A0= 0, which give us the two middle rows of the truth table. The other four transistors are N-type. They pull down to the ground, i.e. 0. The output wire (A xor B) is at 0 when either the left pair or the right pair are open. The former happens when A = B = 1, and the latter when A0= B0= 1 which give us the last and the first rows of the truth table, respectively. Notice that all four combinations of inputs are mutually exclusive, so if a pair of P-type transistors pull up, no pair of N-type transistors is open to pull down and vice versa; there is no conflict on the output line. Thisstraightforward implementation isneither uniquenor themost economical one, even amongwell-behaved circuits that do not cause any signal degradation (mentioned in section *9.3). The following design fully implements the XOR-gate in only 9 transistors: 206

XOR gate optimized on transistor level At the core, we have symmetrical circuit which is not equivalent to one of basic gates To have output=1, we need one of upper pairs open: (A&B =1 | A &B=1) To have output=0, we need one of lower pairs open: (A&B=1 | A &B =1) 12 transistors

XOR gate optimized: second try Much harder to understand

How it works? Consider B=0 This closes T0 and T7 directly, and opens T1 Open T1 opens T3 and closes T6 Transistors T2,4,5,8 form a pair of NOT gates Output will be (A 0)=A Case B=1 is described in tome.pdf

Pass transistor logic (PTL)

9.2 Transistor From theinception of conventional computer architecturethat datesback tothefirst general-purposeENIAC computer in the1940sa controlled switch hasfirmly held itsplaceasthebasic building block of all computer hardware. A simple example of switch functionality is the push-button used to control a door-bell. This has two terminals and is operated by hand. When it is pressed down it connects the two terminals together and completes the circuit. When the button is released, a spring pushes the terminals apart and the circuit is broken. An electronic switch is different from a mechanical switch in one important aspect: it is controlled by a signal, rather than by a human hand. An electronic switch has a third, control, terminal, which, depending on the binary value asserted on it, connects or disconnects the other two. The control terminal must not be allowed to float, since under such conditions, the "door bell" will ring sporadically, and at unpredictable times. The value 1 could be used to close the switch and 0 to open it it, or the other way around: both kinds of switch are used in the technology, and besides they are used in pairs in the same design. Wehavejust described in simpletermstheworkingof amodern MOSFET transistor, thebasicbuildingblock of the silicon chips found in current computers, mobile phones, washing machines, spacecraft anywhere that digital data is to be manipulated. In our circuit diagrams we will represent transistors using the following symbols3: There are two types of transistor: the N-type and the P-type. Each type of transistor has three terminals known as the source, the gate and the drain. The source and the drain are the input and output terminals for the switch respectively. The gate is a terminal used for the control signal. The two types of transistor are distinguished by the way they respond to control signals. TheN-typetransistor is opened by asserting 1 on the gate: this connects the source to the drain. When the signal on the gate is 0, the route from source to drain is blocked. We say that the N-type transistor is open when the gate is up (i.e. equals 1) and closed when the gate is down (i.e. equals 0). A P-type transistor acts in a similar fashion, except that it is open when the gate is down and closed when the gate is up. The situation is completely symmetrical. In circuit diagrams the names of the terminals are not normally written down. The symbol leaves no doubt as to which of the three terminals of a transistor is connected to the gate, and the little arrow between the two other terminals always points from sourceto drain. To see which typethetransistor is, weobservethat the P-type has a little circle on its gate terminal. Thetransistor actsasa purefunction of itsinputs: thesignal at thedrain dependson thesignalson thegate and source at the same moment in time4. To better understand how the output from a transistor depends Floating signals upon the signals asserted on its two inputs we may use truth tables familiar from elementary logic, listing the output of a device against all possible combinations of the input values. Here is one for the N-type transistor: N-type truth table P-type truth table gate 0 0 0 1 1 1 source 0 1 Z 0 1 Z drain Z Z Z 0 1 Z 3these symbols are not the most common ones, but we will use the notation employed by the Logisim logic simulation package, because all of our examples will be run on Logisim. If you are curious about the international standard symbols for devices you may find them in public domain reference materials. 4ignoring for now any delay in opening or closing the transistor, and in propagating a signal from source to drain Also, you should avoid connecting conflicting outputs But connecting floating output to non-floating one is OK Actually, NOT gate uses exactly this kind of connection Generally, you should avoid floating input on transistor gates 199

Pull resistor Gives sort of default value to circuit output I.e. when output floats, pull resistor pulls it to 0 If we connect it to PWR, it will pull it to 1

NAND gate using pull resistor

Why not use pull resistors everywhere? They are slow They consume power

10.7 Controlled buffer and transmission gate In the previous section we assumed that a Level 1 component had the ability to assert 1 or disconnect, and we relied on the pull resistor to provide the value 0 when the device actually disconnected. A much more common situation at Level 1 is when several devices can assert a value on the same input, and the designer wishes to choose which one will succeed in doing it (recall that asserting different values on the same input at the same time is forbidden by the rules of Platform 0). This is achieved by using a controlled bufferwith the following truth table : Controlled buffer Ctrl 0 0 1 1 X 0 1 0 1 Y Z Z 0 1 This device allows to controllably pass X to Y Actual buffers are bidirectional (signal and even floating value passes also from Y to X) But Logisim simulates them as unidirectional Recall, that Z stands for floating . There is a version of control buffer which is always open (Ctrl=1). It is called simply the buffer. It does not use the control signal and is fully analogous to a chain of two inverters. Smarter implementation known as transmission gate Less signal degradation Here is an (obvious) Platform 0 implementation of the controlled buffer: The N-type transistor opens when Ctrl is at 1, and lets X through to the output. If Ctrl is 0, the transistor is closed and Y is isolated from X. A set of n controlled buffers may be used to select which one out of the n devices is allowed to assert its signal on an input to another device. We could leave the analysis of the controlled buffer at that in the idealised world of electronics, but we must not forget about the limits that any idealisation imposes. An N-type transistor in PTL (which is what we have above) is, as we know, subject to signal degradation described in section *9.3 when X is high. The way to avoid it is to use what is known as the transmission gate: The transmission gate is two transistors, an N-type and a P-type, connected in parallel (sink to sink and drain to drain), with the two gates driven at all times by opposite values. The triangular component at the bottom of the diagram is the standard inverter, which delivers inverted Ctrl to the gate of the P-type transistor. When the N-type gate is open, so is the P-type and the same is true when the gate is closed. When the transistors are open, any value of X makes one of the transistors pull Y hard towards it and the other transistor does so less effectively. As a result a weak conflict ensues (of the same kind as we described in theanalysis of the9 transistor XOR gateon page207). Thetransistor operating in perfect conditionseasily wins the weak conflict and the observable output in such a case shows no significant signal degradation. Our chosen circuit simulator, Logisim, treats transistors, and by extension transmission gates, as unidirec- tional devices: thesignal iscopied from the input tothe output only. In real lifean open CMOStransistor is bi-directional. This means that when it opens it can be thought of (ignoring signal degradation) as plain wire conducting signals between the source and the drain both ways. A transistor/ transmission gate will even pass a floating signal in either direction in the absence of an active drive, just as the wire would. This should be borne in mind whenever transmission gates are used in complex designs. By contrast, wewill only requirethecontrolled buffer (and never atransmission gateactingbidirectionally) in therest of thetext, and bufferswill only beused with a non-floating input signal. TheLogisim sinadequate simulation of transistors should, however, be born in mind when attempting some of the circuit-design exercises that accompany the book. 210