Architectural Aid to Secure Systems Engineering: Paging and Virtual Memory
Architectural aid plays a crucial role in securing systems engineering. This session delves into the concepts of paging and virtual memory, highlighting the fundamentals, techniques, and addressing aspects involved. From understanding page frames to implementing demand paging, this session provides valuable insights into optimizing memory usage and enhancing system performance.
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Presentation Transcript
Information Security - 2 Topic: Architectural Aid to Secure Systems Engineering V. Kamakoti RISE LAB, Department of Computer Science and Engineering IIT Madras SESSION 13: PAGING AND VIRTUAL MEMORY
Virtual Memory and Paging It is always enough if the next instruction to be executed and the data needed to execute the same are available in the memory. The complete code and data segment need not be available. Use of paging to realize the stuff! By using segmentation the processor calculates an 32-bit effective address.
Paging fundamentals Each page is 4096 bytes Physical RAM has page frames like photo frames, which is also 4096 bytes. A page is copied into the page frame, if needed and removed to accommodate some other page. By this, a 4 GB code can run on a 128MB physical memory This is also called demand paging.
Paging Technique 32-bit Address 12-bit address + Page Directory Stored In RAM (Location of every page in RAM if it is loaded, else INVALID) 20-bit address
Protected Mode Addressing with paging 10 10 12 DIR OFFSET TABLE PAGE FRAME PAGE TABLE PAGE DIRECTORY PHYS ADDRS 4KB entries with 4 bytes per entry 4KB entries with 4 bytes per entry PG TBL ENTRY DIR ENTRY If 20 bytes are used as a single level paging then page table alone is 4 MB which is inefficient. So two level paging. Develop the page table on demand CR3 REG TLB s used to improve performance Dirty bit accommodated in each page entry
End of Session-13 Thank You
