Architectural Aid to Secure Systems Engineering: Task Switching and Interrupt Service

Architectural Aid to Secure Systems Engineering: Task Switching and Interrupt Service
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Task switching and interrupt handling are crucial aspects of secure systems engineering. This session delves into how architectural aids facilitate seamless task switching, ensuring efficient system processes. Learn about task state segments, interrupt descriptor tables, and the handling of various interrupts in this insightful exploration.

  • Secure Systems Engineering
  • Task Switching
  • Interrupt Service
  • Architectural Aid
  • System Processes

Uploaded on Mar 02, 2025 | 0 Views


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  1. Information Security - 2 Topic: Architectural Aid to Secure Systems Engineering V. Kamakoti RISE LAB, Department of Computer Science and Engineering IIT Madras SESSION 14: TASK SWITCHING AND INTERRUPT SERVICE

  2. Task Switching Every process has an associated Task State Segment, whose starting point is stored in the Task register. A task switch happens due to a jmp or call instruction whose segment selector points to a Task state segment descriptor, which in turn points to the base of a new task state segment

  3. Task State Segment

  4. Task Switching There are different types of descriptors in a Descriptor table. One of them is a task state segment descriptor. jmp 0x10:<don t care> and that 0x10 points to a TGD, then the current process context is saved and the new process pointed out by the task state segment descriptor is loaded. A perfect context switch. TSS descriptor only in a GDT.

  5. Task Switching process

  6. Interrupt Handling Processor generates interrupts that index into a Interrupt Descriptor Table, whose base is stored in IDTR and loaded using the privileged instruction LIDT. The descriptors in IDT can be Interrupt gate: ISR handled as a normal call subroutine uses the interrupted processor stack to save EIP,CS, (SS, ESP in case of stack switch new stack got from TSS). Task gate: ISR handled as a task switch Needed for stack fault in CPL = 0 and double faults.

  7. Interrupt Handling Processor handles a total of 255 interrupts 0-31 are used by machine or reserved 32-255 are user definable 0 Divide error, goes to first descriptor in IDT 1 Debug 8 Double Fault 12 Stack Segment fault 13 General Protection Fault 14 Page Fault

  8. End of Session-14 Thank You

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