ARM Bus Technology in Embedded Systems
Explore the intricacies of ARM bus technology in embedded systems, covering topics such as the general bus structure, classes of devices, bus architecture levels, and peripheral buses. Learn about the ARM Local Bus for on-chip memory controllers and the Peripheral Bus for on-chip peripheral functions.
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Subject Name : Embedded Systems Department of : ECE Created By: Dr. Ravinder Nath Rajotiya JIMS Engineering Management Technical Campus Greater Noida, UP -201308 (Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Subject : Embedded Systems Topic: : ARM Bus
ARM Bus Technology Peripheral Interconnect (PCI) bus, this type of technology is external or off-chip. Component On-chip bus that is internal to the chip and that allows different peripheral devices to be interconnected with an ARM core.
Classes of devices attached to the bus. 1. Bus master(ARM processor core) a logical device capable of initiating a data transfer with another device across the same bus. 2. Bus slaves(Peripherals) logical devices capable only of responding to a transfer request from a bus master device. .
Bus has two architecture levels physical level that covers the electrical characteristics and bus width (16, 32, or 64 bits). Second level deals with protocol the logical rules that govern the communication between the processor and a peripheral.
ARM External Bus Figure shows the data bus and bus splitter
Local Bus The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the ARM
Peripheral Bus Peripheral Bus (APB, a compatible superset of ARM s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2141/24/6/8 configures the ARM7TDMI-S processor in little-endian byte order.
ARM High Performance Bus(AHB) AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than the interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.
