ARM Cortex-M Programming: Interrupts, Exceptions, and Priorities
Explore interrupt handling and exception programming in ARM Cortex-M processors, including interrupt vector tables, interrupt priorities, and control registers. Learn about the differences between polling and interrupts and the stack frame upon interruption.
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Chapter 6 Interrupt and Exception Programming 1
Interrupt Vector Table for ARM Cortex-M Interrupt # Interrupt Memory Location (Hex) 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 Stack Pointer initial value Reset NMI Hard Fault Memory Management Fault Bus Fault 1 2 3 4 5 6 Usage Fault (undefined instructions, divide by zero, unaligned memory access,...) Reserved Reserved Reserved Reserved SVCall Debug Monitor Reserved PendSV SysTick IRQ 0 for peripherals IRQ 1 for peripherals IRQ 239 for peripherals 7 8 9 10 11 12 13 14 15 16 17 255 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000040 0x00000044 0x000003FC 4
Interrupt Priority for ARM Cortex-M Interrupt # 0 1 2 3 4 5 6 Interrupt Priority Level Stack Pointer initial value Reset NMI Hard Fault Memory Management Fault Bus Fault -3 Highest -2 -1 Programmable Programmable Programmable Usage Fault (undefined instructions, divide by zero, unaligned memory access,....) Reserved Reserved Reserved Reserved SVCall Debug Monitor Reserved PendSV SysTick IRQ 0 for peripherals IRQ 1 for peripherals IRQ 239 for peripherals 7 8 9 10 11 12 13 14 15 16 17 255 Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable 8
CONTROL Register in ARM Cortex-M4 nPRIV (Privilege): 0: 1: Active Stack Pointer (ASP): 0: 1: Floating Point Context Active (FPCA) 0: No floating point context active. 1: Floating point context active. Defines the Thread mode privilege level Privileged Unprivileged Defines the currently active stack pointer (ASP = SPSEL) MSP is the current stack pointer. PSP is the current stack pointer. 9
Processor Modes and Stack Usage in ARM Cortex-M Processor Mode Thread Handler Note: In Thread mode, use bit 1 of the Control register to select MSP or PSP for stack pointer. Software Applications Stack Usage MSP or PSP MSP ISR for Exceptions and IRQs 10
Privileged level Execution and Processor Modes in ARM Cortex-M Processor Mode Thread Software Applications Privilege level Privileged and Unprivileged Always Privileged Handler Note: In Thread mode, use bit 0 of the CONTROL register to select Privileged or Unprivileged ISR for Exceptions and IRQs 11
Processor Mode, Privilege, and Stack in ARM Cortex Mode Handler Handler Privilege Privileged Unprivileged Stack Pointer Main Any Typical Example usage Exception Handling Reserved since Handler is always Privileged Operating system kernel Thread Thread Thread Thread Privileged Privileged Unprivileged Unprivileged Main Process Main Process Application threads 12
Special function registers of ARM Cortex-M Register name MSP (main stack pointer) PSP (processor stack pointer) Privilege Usage Privileged Privileged or Unprivileged Privileged Privileged or Unprivileged Privileged Privileged Privileged Privileged Privileged Privileged PSR (Processor status register) APSR (application processor status register) ISPR (interrupt processor status register) EPSR (execution processor status register) PRIMASK (Priority Mask register) FAULTMASK(fault mask register) BASEPRI (base priority register) CONTROL (control register) Note: We must use MSR and MRS instructions to access the above registers 13
IRQ assignment in KL25Z of FRDM board INT# 1-15 16 17 18 19 20 21 22 23 24 25 26 27 28 IRQ# None 0 1 2 3 4 5 6 7 8 9 10 11 12 Vector location 0000 0000 to 0000 003C 0000 0040 0000 0044 0000 0048 0000 004C 0000 0050 0000 0054 0000 0058 0000 005C 0000 0060 0000 0064 0000 0068 0000 006C 0000 0070 Device CPU Exception (set by ARM) DMA DMA DMA DMA ---- FTFA PMC LLWU I2C0 I2C1 SPI0 SPI1 UART0 15
IRQ assignment in KL25Z of FRDM board (Cont.) INT# 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 IRQ# 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Vector location 0000 0074 0000 0078 0000 007C 0000 0080 0000 0084 0000 0088 0000 008C 0000 0090 0000 0094 0000 0098 0000 009C 0000 00A0 0000 00A4 0000 00A8 0000 00AC 0000 00B0 0000 00B4 0000 00B8 0000-00BC Device UART1 UART2 ADC0 CMP0 TPM0 TPM1 TPM2 RTC RTC PIT ----- USB OTG DAC0 TSI0 MCG LPTMR0 ----- I/O PORTA I/O PORTD 16
I/O Interrupt Trigger D19 D18 D17 D16 1 0 0 0 Interrupt when logic zero (Active Low-level). 1 0 0 1 Interrupt on rising edge. 1 0 1 0 Interrupt on falling edge. 1 0 1 1 Interrupt on either edge. 1 1 0 0 Interrupt when logic one (Active High-level) 23
UART Control 2 (UARTx_C2) register Field Bit Description TIE D7 Transmit Interrupt Enable bit. Used for interrupt-driven UART. 0 = TDRE Interrupt Request is disabled. 1 = TDRE Interrupt Request is enabled. Transmission Complete Interrupt Enable bit. Used for interrupt-driven UART. 0 = TC Interrupt Request is disabled. 1 = TC Interrupt Request is enabled. Receiver Full Interrupt Enable bit. Used for interrupt-driven UART. 0 = RDRF Interrupt Request is disabled. 1 = RDRF Interrupt Request is enabled. Idle Line Interrupt Enable bit. Used for interrupt-driven UART. 0 = IDLE Interrupt Request is disabled. 1 = IDLE Interrupt Request is enabled. Transmitter Enable bit. We must enable this bit to transmit data. 0 = Transmitter is disabled. 1 = Transmitter is enabled. Receiver Enable bit. We must enable this bit to receive data. 0 = Receiver is disabled. 1 = Receiver is enabled. Used for wake-up condition in stand-by mode. See the KL25Z manual. 0 = Normal operation 1 = RWU is enabled. Used for break bit. See the KL25Z manual. 0 = No break character 1 = Transmit break character TCIE D6 RIE D5 ILIE D4 TE D3 RE D2 RWU D1 25 SBK D0
