ATE Test Time Reduction: Scaling Voltage and Frequency
Explore how to reduce test time in Automated Test Equipment (ATE) by adjusting voltage and frequency, with a focus on power constraints and clock cycles. Proposed methods include optimizing supply voltage and utilizing aperiodic clocks to minimize test duration while staying within power limits. Research findings suggest a lower bound for test time reduction and validate the effectiveness of aperiodic clock testing.
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Presentation Transcript
ATE Test Time Reduction by Scaling Voltage and Frequency Praveen Venkataramani Advisor: Vishwani D. Agrawal
Problem statement 2 Test is not free* Test time is proportional to test cost Scan based test clock period is limited by the maximum power consumed during a clock cycle. Test cycles can be large, and in addition to the large volume of test vectors increases the total test time. Reduce test time without exceeding power budget *Arthur George Test is it, or is it not, value added? Keynote, VTS 2014 TTTC Doctoral Thesis Contest 2014 6/5/2025
Test time theorem 3 For power constrained testing where the peak power during any clock cycle must not exceed the rated power of the device, the test time has a lower bound ??????(????) ????(?????) ??????(????) ???? ?? = where ETOTAL(test)is the total energy consumed during the entire test, PMAX(rated) is the maximum rated power for the device, PAVG is the average power of the entire test and TT is the total test time. TTTC Doctoral Thesis Contest 2014 6/5/2025
Proposed methods 4 Lower bound Optimum supply voltage Aperiodic clock TTTC Doctoral Thesis Contest 2014 6/5/2025
ATE example Periodic clock 5 16.5 s Test clock period = 500 s, Total number of cycles = 33. TTTC Doctoral Thesis Contest 2014 6/5/2025
ATE example Aperiodic clock 6 16.5 s Test clock period = 200ns, 300ns, 410ns, 500ns, Total number of cycles = 58. TTTC Doctoral Thesis Contest 2014 6/5/2025
Optimum voltage- s298 7 TTTC Doctoral Thesis Contest 2014 6/5/2025
Conclusion 8 A new lower bound to reduce test time is proposed. Methods were verified through simulation and experiment on the ATE. Aperiodic clock test provides lower test time at any voltage as long as there are some test cycles that are power constrained. According to the test time theorem, aperiodic clock test time will always be less than or equal to the periodic clock test time. TTTC Doctoral Thesis Contest 2014 6/5/2025
Future work 9 Aperiodic clock is not limited to ATE. Use of aperiodic test with on chip clock must be studied. Implementation of the proposed methods for delay testing. Dynamic voltage management. Effect on leakage power must be studied when using the proposed methods. Implementation using modern technologies TTTC Doctoral Thesis Contest 2014 6/5/2025
