Binary Logic and Logic Gates Overview for Digital Circuits

COMP541 Combinational Logic - I Montek Singh Aug {28, 30}, 2017

Today Basics of digital logic (review) Basic gates Combinational logic Various representations Boolean algebra Truth tables Karnaugh Maps ( K-Maps ) Circuit schematic diagrams Hardware Description Languages (HDL) 2

Binary Logic Binary variables Can be 0 or 1 (True or False, low or high) Variables named with single letters in examples Really use words when designing circuits 3

Logic Gates Perform logic functions: inversion (NOT), AND, OR, NAND, NOR, etc. Single-input: NOT gate buffer (non-inverting) Two-input: AND, OR, XOR, NAND, NOR, XNOR Multiple-input Most 2-input gates also have multi-input flavors 4

Single-Input Logic Gates BUF NOT A Y A Y Y = A Y = A A 0 1 Y 0 1 A 0 1 Y 1 0 5

Two-Input Logic Gates OR AND A B A B Y Y Y = A + B Y = AB A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 6

More Two-Input Logic Gates XOR NAND NOR XNOR A B A B A B A B Y Y Y Y Y = A + B Y = AB Y = A + B Y = A + B A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1 7

More Two-Input Logic Gates XOR NAND NOR XNOR A B A B A B A B Y Y Y Y Y = A + B Y = AB Y = A + B Y = A + B A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1 8

Multiple-Input Logic Gates NOR3 A B C Y Y = A+B+C A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 0 0 0 0 0 0 0 9

Multiple-Input Logic Gates NOR3 A B C Y Y = A+B+C A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 0 0 0 0 0 0 0 10

NAND is Universal Can express any Boolean Function 11

Using NAND as Invert-OR DeMorgan s Law: AB= A+B Also reverse inverter diagram for clarity 12

NOR Also Universal Dual of NAND: also can express any Boolean func 13

Representation: Schematic Schematic is short for schematic diagram Simply means a drawing showing gates (or more complex modules) and wire connections More complex modules are usually shown as black boxes 14

Representation: Boolean Algebra More on this next class = + F X Y Z 15

Representation: Truth Table 2n rows: where n is # of variables 16

Schematic Diagrams Can you design a Pentium or a graphics chip that way? Well, yes, but diagrams are overly complex and hard to enter These days people represent the same thing with text You can call it code, but it is not software! More precisely, it is a textual description 17

Hardware Description Languages Main ones are Verilog and VHDL Others: Abel, SystemC, Handel Origins as testing languages To generate sets of input values Levels of use from very detailed to more abstract descriptions of hardware 18

Design w/ HDL Two leading HDLs: Verilog developed in 1984 by Gateway Design Automation became an IEEE standard (1364) in 1995 evolved into SystemVerilog in 2002 VHDL Developed in 1981 by the Department of Defense Became an IEEE standard (1076) in 1987 Most (all?) commercial designs built using HDLs We will use Verilog/SystemVerilog 19

Uses of HDL Simulation Defines input values applied to the circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Synthesis Transforms HDL spec into a circuit-level implementation HDL is transformed into a netlist Netlist = a list of gates and the wires connecting them Just a textual description instead of drawing IMPORTANT: When describing circuits using an HDL, it is critical to think of the hardware the specification should produce. 20

Verilog Module Code always organized in modules remember: this is not really code , but a description of the hardware or hardware s behavior Represent a logic box With inputs and outputs a b c Verilog Module y 21

Example module example(input wire a, b, c, output wire y); *** HDL DESCRIPTION HERE *** endmodule a b c Verilog Module y 22

Levels of Verilog Several different levels (or views ) Mainly two types: Structural or Behavioral Structural: Describe the physical structure of the hardware Typically, gates/modules and wires that connect them Behavioral: Describes the algorithmic behavior of the hardware E.g., Output X = Y + Z 23

Example 1 Output is 1 when input < 011 Figure (b) is called a Karnaugh Map (or K-Map ) graphical representation of truth table: n-dimensional cube Figure (c) is a sum-of-products implementation AND-OR, implemented as NAND-NAND 24

Structural Verilog Explicit description of gates and connections Textual form of schematic Specifying netlist netlist = gates/modules and their wire connections 25

Example 1 in Structural Verilog module example_1( input wire X, input wire Y, input wire Z, output wire F ); Can also be written as: input wire X, Y, Z, output wire F wire X_n, Y_n, Z_n, f1, f2; f1 not X_n g0(X_n, X), g1(Y_n, Y), g2(Z_n, Z); Y_n endmodule nand X_n g3(f1, X_n, Y_n), g4(f2, X_n, Z_n), g5(F, f1, f2); actually, just a NAND gate f2 26

Slight Variation Gates not named module example_1( input wire X, input wire Y, input wire Z, output wire F ); wire X_n, Y_n, Z_n, f1, f2; not(X_n, X); not(Y_n, Y); not(Z_n, Z); Observe two orthogonal changes: each gate is declared using a separate not or nand declaration gate instances are not named nand(f1, X_n, Y_n); nand(f2, X_n, Z_n); nand(F, f1, f2); endmodule 27

Explanation Each of these gates is an instance Like object vs class In first example, they had names not g0(X_n, X), In second example, no name not(X_n, X); Why can naming an instance be useful? 28

Gates Standard set of gates available and, or, not nand, nor xor, xnor buf 29

Dataflow Description (Behavioral) module example_1( input wire X, Y, Z, output wire F ); assign F = (~X & ~Y) | (~X & ~Z); Basically a logical expression endmodule No explicit gates rewritten using sum-of-products (AND-OR) style 30

Conditional Expressions Useful for: describing multiplexers combinational logic in an if-then-else style Example: Output 1 if input is less than 3 Notice alternate specification module example_2( input wire[2:0] A, output wire F ); // A is a 3-bit number assign F = (A < 3) ? 1 : 0; // or assign F = (A<3); endmodule 31

Abstraction Using the digital abstraction we have been thinking of the inputs and outputs as True or False 1 or 0 What are they really? 32

Logic Levels Define discrete voltages to represent 1 and 0 For example, we could define: 0 to be ground or 0 volts 1 to be VDD or 5 volts What about 4.99 volts? Is that a 0 or a 1? What about 3.2 volts? 33

Logic Levels Define a range of voltages to represent 1 and 0 Define different ranges for outputs and inputs to allow for noise in the system What is noise? 34

What is Noise? Anything that degrades the signal E.g., resistance, power supply noise, coupling to neighboring wires, etc. Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts Noise Driver Receiver 5 V 4.5 V 35

The Static Discipline Given logically valid inputs, every circuit element must produce logically valid outputs Discipline ourselves to use limited ranges of voltages to represent discrete values 36

Logic Levels NMH = VOH VIH NML = VIL VOL 37

DC Transfer Characteristics (See textbook for characteristics of an inverter) Ideal Buffer: Real Buffer: V(Y) V(Y) A Y VDD VOHVDD VOH Unity Gain Points Slope = 1 VOL V(A) V(A) VOL 0 0 VDD / 2 VDD VIL VIH VDD VIL, VIH NMH , NML < VDD/2 NMH = NML = VDD/2 38

VDD Scaling Chips in the 1970s and 1980s were designed using VDD = 5 V As technology improved, VDD dropped Avoid frying tiny transistors Save power 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, 39

Logic Family Examples Logic Family VDD VIL VIH VOL VOH TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4 CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84 LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4 LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7 40

Next Class Boolean Algebra Synthesis of combinational logic 41