Branch-Aware Loop Mapping on Coarse-Grained Reconfigurable Accelerators
Increase performance at lower power vs. utilization with hardware accelerators like DSPs, GPUs, FPGAs, and CGRAs. Learn about branch divergences' impact on resource utilization in accelerators, control flow acceleration, and the benefits of coarse-grained reconfigurable accelerators. Explore loop acceleration, modulo scheduling, predication techniques, and dual-issue architecture for optimizing accelerator performance.
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Presentation Transcript
Branch-Aware Loop Mapping on Coarse-Grained Reconfigurable Accelerators Mahdi Hamzeh, Aviral Shrivastava, and Sarma Vrudhula School of Computing, Informatics, and Decision Systems Engineering Arizona State University
Improve performance at the pace of transistor density increasing 2/15 Source: Intel
Goal: Increase performance at lower power vs. utilization Power Efficiency Hardware accelerators DSPs GPUs FPGAs General purpose processors CGRAs Flexibility 3/15
Branch divergences damage resource utilization in accelerators Time A A A B B C B C C D D D 4/15
Coarse-grained reconfigurable accelerators: a promising solution for high performance, power, and utilization 7/15
Loop Acceleration and Modulo Scheduling 1 2 1 2 3 4 4 3 a a a b b b II c c c d d d b f f e e g g b 8/15
Partial Predication b a h a a b b a h c c h h ?? ?? ?? ?? II e e c f f 9/15
Full Predication a b h a a b b h h a h e b c c ? e b II b a ? e c e b a f f e 10/15
Dual Issue Architecture 11/15
How to map kernels on Dual Issue CGRA b a h h a a b b a b II a b c c c h ?? e e ?? e f f f 12/15
Summary Performance improvement using software accelerators such as CGRAs Control flows are common in benchmarks Most accelerators use classic predication scheme for accelerating loops with conditional Acceleration of loops with divergence in CGRAs, opportunities and challenges Dual issue scheme: potential performance gain and compiler challenges 15/15
