Capturing FPGA Design with VHDL - Structured Digital Design Overview
"Learn about capturing FPGA design using VHDL in this structured digital design overview. Covering topics such as combinational versus sequential design, state machines, signal versus variables, and more. Dive into the world of hardware programming and advanced VHDL concepts."
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Presentation Transcript
Hardware Programming HWP01 capturing a FPGA design with VHDL
Planning: theory Third week Combinational versus sequential design Concurrent and sequential code First week Introduction digital systems Structured digital Design RTL Fourth week Components Generics Fifth week Introduction to state machines Designing state machines Advanced VHDL design Second week Introduction VHDL Code structure and data types Design verification HR EAS ELE HWP01 WK1 V1.0 2
Agenda Discussion of previous week Component instantiating Generics HR EAS ELE HWP01 WK1 V1.0 3
Signals versus variables SIGNAL properties: Can ONLY be declared outside a PROCESS but can be used within a PROCESS Within sequential code the signal is not updated immediately (at the end of the PROCESS) Only a single assignment is allowed to a signal in the whole code (multiple assignments in PROCESSES are fine, but only the last one will be effective!) VARIABLE properties: Can ONLY be declared inside a PROCESS Is updated immediately and can be used in the next line of code Multiple assignments are not a problem HR EAS ELE HWP01 WK1 V1.2 4
Agenda Discussion of previous week Component instantiating Generics HR EAS ELE HWP01 WK1 V1.0 5
Putting it together HR EAS ELE HWP01 WK1 V1.2 6
Create (separately) validated components Entity Architecture Entity Architecture HR EAS ELE HWP01 WK1 V1.2 7
Add components to your top level design Top Level Design: multiply_2hexandDisplay.vhd HR EAS ELE HWP01 WK1 V1.2 8
Instantiating components HR EAS ELE HWP01 WK1 V1.2 9
Agenda Discussion of previous week Component instantiating Generics HR EAS ELE HWP01 WK1 V1.0 10
Generic statements Generic values are used for declaring global constants in a component What is the use of generics? For more information on generics and what else they are capable of, see CH 6.7 HR EAS ELE HWP01 WK1 V1.2 11
Voorbeeld Generics With value Without value HR EAS ELE HWP01 WK1 V1.2 12
Summary Remember the differences between signals and variables Components are pre-validated VHDL library elements used to reduce development time of new products. HR EAS ELE HWP01 WK1 V1.2 13
