Clock Domains and Operating Conditions
In synchronous logic design, clock domains play a crucial role in ensuring proper data synchronization. Explore the concept of clock domains, clock domain crossings, and operating conditions such as PVT for static timing analysis and power analysis.
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Presentation Transcript
PRESENTED BY PRESENTED BY CHETHAN M CHETHAN M
CLOCK DOMAIN CLOCK DOMAIN In synchronous logic design, a periodic signal latches the new data computed into the flip-flops. A clock typically feeds a number of flip-flops. The set of flip-flops being fed by one clock is called its clock domain. Below Figure depicts the flip-flops along with the two clock domain.
Any data paths that start from one clock domain and end in the other clock domain, then the two clock domains are independent of each other which means that there is no timing path that starts from one clock domain and ends in the other clock domain. there are data paths that cross between clock domains shown in below figure, a decision has to be made as to whether the paths are real or not. Fig: clock domain crossing
A clock domain crossing can occur both ways, from USBCLK clock domain to MEMCLK clock domain, and from MEMCLK clock domain to USBCLK clock domain. Fig: Mutually-exclusive clocks The clock domain with two clocks are mutually exclusive if only one clock is activate at one time as shown above.
OPERATING CONDITIONS OPERATING CONDITIONS An operating condition is defined as a combination of Process, Voltage and Temperature (PVT). Cell delays and interconnect delays are computed based upon the specified operating condition. Operating conditions is considered for following static timing analysis
STANDARD OPERATING CONDITIONS FOR STA: WCS (Worst-Case Slow): Process is slow, temperature is highest (say 125C) and voltage is lowest (say nominal 1.2V minus 10%). TYP (Typical): Process is typical, temperature is nominal (say 25C) and voltage is nominal (say 1.2V). BCF (Best-Case Fast): Process is fast, temperature is lowest (say -40C) and voltage is highest (say nominal 1.2V plus 10%). STANDARD OPERATING CONDITIONS FOR POWER ANALYSIS: ML (Maximal Leakage): Process is fast, temperature is highest (say 125C) and the voltage is also the highest (say 1.2V plus 10%). This corner corresponds to the maximum leakage power.
TL (Typical Leakage): Process is typical, temperature is highest(say 125C) and the voltage is nominal (say 1.2V). This refers to the condition where the leakage is representative for most designs since the chip temperature will be higher due to power dissipated in normal operation
