Co-Design Challenges in Heterogeneous Integration

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Notice: The views and conclusions expressed in this presentation do not necessarily reflect the full views of the participants or of their companies. Co-Design Andrew B. Kahng, UC San Diego CSE and ECE Depts. http://vlsicad.ucsd.edu/~abk Co-Chair: Chris Bailey

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Co- -Design Roadmap Scope Design Roadmap Scope Co Design automation tools, methodologies and enablements to support HI Supplier industry: Electronic Design Automation Design automation tools and methodologies Bridge IC, Package, Board tool chains Bridge system, architecture, layout, signoff Bridge specification, synthesis, analysis, verification Modeling and simulation: Chris Bailey in Session 4 this afternoon Heterogeneous integration multi-everything physics, scale, domain, hierarchy Design enablements Design kits attributes of co-integration technology Encapsulations to enable co-integration, interoperability within package Roadmap: Requirements and Potential Solutions out to time horizon of HIR

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Heterogeneous Integration: Heterogeneous Integration: Adoption is Value Adoption is Value- -Driven Driven Decreased Product Cost Co-Design? Co-Design? Increased Product Quality Decreased NRE Schedule, Effort Co-Design?

Work in Progress. Please do not distribute without permission of HIR IRC Chairs HI Co- -Design Design Challenges Challenges: : Cost, Quality, Schedule/Effort Cost, Quality, Schedule/Effort HI Co Decreased Product Cost Design Space Exploration Optimizers: partition, floorplan, IO, P/G, clock, high-speed interconnect Tools, Automations Standards (techno, interop wrappers) Methodology (analyses, signoff) Increased Product Quality Decreased NRE Schedule, Effort

Work in Progress. Please do not distribute without permission of HIR IRC Chairs HI Co- -Design Design Challenges Challenges: : Cost, Quality, Schedule/Effort Cost, Quality, Schedule/Effort + Users + Systems HI Co + Users + Systems Decreased Product Cost Design Space Exploration Optimizers: partition, floorplan, IO, P/G, clock, high-speed interconnect Tools, Automations Standards (techno, interop wrappers) Methodology (analyses, signoff) Architects ICs to integrate Companies with IPs and/or Systems Increased Product Quality Decreased NRE Schedule, Effort Drivers Benchmarks

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Co- -Design Design Potential Solutions: Standards Potential Solutions: Standards Need interoperability specs for whatever is co-integrated inside package Interfaces Today: HBM, HMC, Memory-Logic Next: RF links, high-speed serial interfaces Reference flows, chassis to verify interface spec Wrappers Power integrity Thermal, thermomechanical Signal integrity EMI Signoff Analyses / Methodology Timing across multiple die Power, thermal (multiple die operating asynchronously, charge sharing in decap, ) Co

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Co- -Design Design Potential Solutions: Tools Potential Solutions: Tools More analog in IC tools, especially router e.g., buses, differential signals, P/G network Timing analysis and signoff with incomplete models Beyond orchestration of 2D IC tools incremental value must be clear! Floorplanning, IO assignment, bus planning e.g., with passive interposer Power delivery and clock delivery planning e.g., many DC-DC converters, DLLs Co

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Example: Unified Planning Tool (Die Example: Unified Planning Tool (Die- -Pkg Pkg- -Pcb Pcb) )

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Co- -Design Design Potential Solutions: Tools Potential Solutions: Tools More analog in IC tools, especially router e.g., buses, differential signals, P/G network Timing analysis and signoff with incomplete models Beyond orchestration of 2D IC tools incremental value must be clear! Partitioning-floorplanning, IO assignment, bus planning e.g., with passive interposer Power delivery and clock delivery planning e.g., many DC-DC converters, DLLs Nuts and bolts Full support for hierarchical design Support for multiple die and technologies Longer term: system-architecture pathfinding cost optimization, IP configuration Even longer: partitioning and covering tools heavy reuse from chiplet catalog And longer: software co-design will likely dominate system value Co

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Tables, Trajectories, Metrics Tables, Trajectories, Metrics Interface standards Wrappers layout, timing, PI/SI, power delivery, thermal, EMI, thermomech Signoffs timing, PI/SI, thermomechanical, reliability, Benchmarks progress of tools, methodologies with respect to Quality, Cost, Effort/Schedule Tools partitioning, routing, unified planning (floorplan, IO, power/clock), signoff analysis, system/architecture pathfinding, partitioning-covering Key metric: Scalability with system complexity Key metric: Quality, Cost, Schedule improvements beyond orchestration of IC tools logic, memory, analog, RF ...

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Co- -Design for Heterogeneous Integration Design for Heterogeneous Integration Fact: Non-emergence of commercial EDA solutions for Co-Design Long history of multi-die integration: MCM, SIP, 3-D / 2.5-D, Small available market mismatches commercial EDA model Fact: Semiconductor technology roadmap established in 1990s 1970s: wild west 1990s: mainstreaming = when NTRS, ITRS were launched Fact: Co-design tools and flows exist today (evidenced by products) Based on existing IC design standards, tool flows, methodologies Key roadmapping questions: What system products will drive creation of new co-design tools/methods? What incremental value will new co-design tools/methods bring to those products? When will answers to the above become apparent? Co

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Cross-TWG Collaboration Priorities Technical Working Groups Aerospace & Defense High performance Computing 3D+2.5D WLP Photonics Test Medical & Health SiP Single & Multi-chip Integrated Power Emerging Devices IoT 5G + RF Interconnect MEMS & sensors Cyber Security Mobile Automotive Simulation Emerging Materials Supply Chain Co-Design LEVEL 1=ABSOLUTELY NECESSARY LEVEL 2= NEED OCCASIONAL SYNCHRONIZATION LEVEL 3= NICE TO KNOW 1 1 1 1 2 Systems and Applications drive need for new co-design technology Test Component + integration technologies Interconnect, integrated power, 3D+2.5D, 1 1 1 1 1 3 1 1 1 2 2 1 1 1 3 2

Work in Progress. Please do not distribute without permission of HIR IRC Chairs Many Thanks To: Many Thanks To: Chris Bailey (co-chair) Antun Domic Xuejun Fan Vassilios Gerousis Puneet Gupta + YOU Ajay Joshi Riko Radojcic Kambiz Samadi Vaishnav Srinivas Brandon Wang Notice: The views and conclusions expressed in this presentation do not necessarily reflect the full views of the participants or of their companies.

Work in Progress. Please do not distribute without permission of HIR IRC Chairs THANK YOU ! THANK YOU !