Component Selection for SDR Applications: Requirements and Considerations
This content explores the key components selection for Software-Defined Radio (SDR) applications, covering ADC, DAC, DSP, FPGA choices, and high-level SDR block diagrams. It delves into the importance of ADC and DAC specifications, DSP and FPGA advantages, and considerations for ADC selection. The discussion highlights the need for configurability and flexibility in SDR designs to meet diverse application requirements effectively.
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Presentation Transcript
RCE-8836206 Radio Signal Processing Lecture 7: Component Selection for SDR Applications 7.1 Generic Requirements 7.2 ADC Selection 7.3 DAC Selection 7.4 DSP Selection 7.5 FPGA Selection 7.6 Summary Source: Altera White Paper, "Architecture and component selection for SDR applications", 2007. 1
7.1 Generic Requirements High-Level SDR Block Diagram 2
High-Level SDR - Most needed in military applications - To position digital-to-analog separation as close as possible to the antenna - Replace analog blocks with reconfigurable digital blocks - Obsolescence-proof radio product - Difficult to achieve with small battery-powered platforms - Cost, power requirements, size, environmental hardening - Requirements vary by application 3
ADC Block - IF frequency selection is important. - Now IF frequency above 500 MHz possible - Still direct sampling of 2-GHz signal no possible - IF frequency depends on ADC capabilities. - IF-subsampling ADC, 100 Msps, 12+ bits, 1-GHz analog input bandwidth, 200-mW power consumption per channel -ADC sampling rate Increases effective SNR Improves sensitivity and dynamic range 5
DAC Block - Transmit IF frequency depends on the baseband circuit capabilities - Transmit IF frequency is limited to about 80 MHz. - Solution (though expensive): integrated interpolation, digital mixer, and the DAC selection of transmit IF up to 400 MHz 6
Advantages of DSP + FPGA Approach - Configurability and flexibility with DSP + FPGA approach -ASIC approach (as in cellphone): no flexibility and configurability but low-cost and low-power 7
7.2 ADC Selection Points to Consider - IF sub-sampling for very high receive IF -Analog bandwidth of the ADC - Tight requirements of the jitter of the ADC clock - Maximum characterized IF frequency -ADC resolution: 12-bit sufficient for most applications 8
7.3 DAC Selection DAC is Used in Tx Chain - Very high transmit IF: not attractive due to power and cost penalties -Above 400 MHz: use analog conversion stage - Sub 100-MHz transmit IF: for signal bandwidth < 25 MHz, use a single mixer for conversion to RF - DAC resolution: 14-bit sufficient for most applications 9
7.4 DSP Selection DSP Requirements 10
DSP Points to Cosider - Processing power, cost, size, power consumption (esp. for handsets) - Packet processing, protocol - Ease of software development - Media processing including video processing - Interfacing between DSP and FPGA: high bandwith & multiple interfaces 11
Task Splitting between DSP and FPGA - DSP Complex algorithm with lower rate-processing tasks - FPGA Simple algorithm but fast processing tasks - Example: initial acquisition of the receive signal To simultaneously find frequency offset, timing recovery, synchronization DSP: calculates the algorithm parameters FPGA: do most of the processing - Example of DSP/FPGA cooridinated tasks Inter-device communications Interrupts 12
7.5 FPGA Selection FPGA Considerations - Modern FPGAs: not just programmable hardware Extensive IP cores, MCU soft cores, reference designs, SoC design methodology, comprehensive design environments - Power consumption, cost, DSP-capability - Candidates for FPGA implementation Digital up and down conversion Pulse shape filtering CDMA bit-level processing OFDM FFT processing Transmit crest factor reduction Decoding: turbo, Viterbi, Reed-Solomon 14
7.6 Summary SDR Component Selection - To be based on the radio requirements - Power consumption and size: important for handsets and portable devices - Cost consideration: important in competitive consumer markets - Development time: mostly in software development so that open-source SW cores are very important. 16
RCE-8836206 Radio Signal Processing Lecture 7: Component Selection for SDR Applications 17
