Correcting 24-Bit Panel Mapping Error for LVDS Serializer
Discover how a mapping error led to loss of Most Significant Bits (MSBs) in a 24-bit panel configuration and learn about the correction process to ensure accurate color representation without artifacts. View the final schematic for the corrected mapping.
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Presentation Transcript
Original Mapping was pulled from NSC/TI Document SNLA014 for 18 & 24 bit connections to the C383/385 LVDS Serializer. The below pattern was mapped. But this map did not match the panel
There are two common 24Bit maps. The TI document only listed one (LDI) but our panel followed a more common (VESA) MAP outlined in RED. We lost the MSB s because every color shifted down two, making the map only usable for 18 bit panels P a n e l Pin # DS90CD38324-bit LDI Pin-Signal 2TxIN5 3TxIN6 4TxIN7 6TxIN8 7TxIN9 8TxIN10 10TxIN11 11TxIN12 12TxIN13 14TxIN14 15TxIN15 16TxIN16 18TxIN17 19TxIN18 20TxIN19 22TxIN20 23TxIN21 24TxIN22 25TxIN23 27TxIN24 28TxIN25 30TxIN26 50TxIN27 51TxIN0 52TxIN1 54TxIN2 55TxIN3 56TxIN4 24-bit VESA RED_1 RED_7 GREEN_2 GREEN_3 GREEN_4 GREEN_0 GREEN_1 GREEN_5 GREEN_6 GREEN_7 BLUE_2 BLUE_0 BLUE_1 BLUE_3 BLUE_4 BLUE_5 BLUE_6 BLUE_7 GND HSYNC VSYNC DEN RED_0 RED_2 RED_3 RED_4 RED_5 RED_6 RED_7 RED_5 GREEN_0 GREEN_1 GREEN_2 GREEN_6 GREEN_7 GREEN_3 GREEN_4 GREEN_5 BLUE_0 BLUE_6 BLUE_7 BLUE_1 BLUE_2 BLUE_3 BLUE_4 BLUE_5 NA HSYNC VSYNC DEN RED_6 RED_0 RED_1 RED_2 RED_3 RED_4 D S 9 0 C 3 8 3
Color Bar test and scope confirmed the mapping error. (Panel Running in 24 bit without artifacts with limited color pallet)
