CSE 140 Midterm 2 Review: Sequential Networks, Memory Components & Finite State Machines

CSE 140 MT 2 Review By Daniel Knapp

Overview Sequential Networks Introduction and memory components Specification, analysis, and implementation Timing Standard Combinational Modules Decoders and Encoders Multiplexers (Mux) and Demultiplexers (Demux) System Design (not heavy focus of MT 2)

Sequential Networks Latches (Level Sensitive) SR Latches, D Latches Flip-Flops (Edge Triggered) D FFs, JK FFs, T FFs Examples of Memory Modules Registers, Shift Registers, Pattern Recognizers, Counters, FIFOs

Latches Basic SR Latch

Latches cont. D Latch (avoids SR 11 input)

Flip-Flops D Flip-Flop (all FFs are edge triggered) State changes every rising edge of the CLK (NS becomes PS)

Flip-Flops cont. JK Flip-Flop (edge triggered)

Flip-Flops cont. T Flip-Flop (edge triggered)

Flip-Flops cont.

Finite State Machines Used to describe circuit behavior over time Mealy- current state and current input; Moore- only current state

Finite State Machines cont. Mealy Machine Moore Machine

Finite State Machines cont. Output of mealy machine is put on the transition, 1/0 Mealy Machine Output of moore machine belongs only to the state, not its transitions Moore Machine

Finite State Machines cont. Be able to draw this table for a state diagram Mealy Machine Moore Machine

Mealy to Moore Conversion

Mealy to Moore Conversion cont. S0_0 S0_0 S0_0 S0_1 S0_1 S1 S0_0 1

Implementation Implementing JK FF with T FF Inputs are J(t), K(t), and Q(t) T(t) is the output of some combinational logic used as input to the T FF to change Q(t) to Q(t+1) Q(t) is also the current output of the design Q(t+1) is the next state

Implementation cont. Good chance you may have something like HW4 prob 5 on the midterm Be able to Create state diagram from a given description Write a state table Write an excitation table which includes specific FF inputs if the problem asks to design using some specific type of Flip-Flops Draw K-maps derived from the excitation table Create a minimum SOP or POS expression for each K-map Draw the logic diagram for the system

Implementation cont. Good chance you may have something like HW4 prob 5 on the midterm Be able to Create state diagram from a given description Write a state table Write an excitation table which includes specific FF inputs if the problem asks to design using some specific type of Flip-Flops Draw K-maps derived from the excitation table Create a minimum SOP or POS expression for each K-map Draw the logic diagram for the system

Timing

Timing cont.

Timing cont.

Timing cont.

Timing cont.

Timing cont. Add in skew This formula is worst case for setup time May be able to decrease clock period if skew is best case (retiming) Worst Case Best Case

Timing cont. Add in skew

Timing cont. When retiming, find max skew tolerable with hold time equation Then plug the skew into the best case scenario for the setup time equation to get an improved clock period

Standard Combinational Modules Commonly used combinational circuits that are more complicated than gates Many of them are used to implement control logic for system design

Decoder

Encoder

Priority Encoder

Multiplexer

Demultiplexer

System Design Focus on understanding the other topics thoroughly and if you have more time, review the system design podcast Better to handle questions from this material on piazza or office hours than at the review session today since the other material would cover the bulk of the points