Design of CMOS Two-Stage Op-Amp Bias Currents
The content delves into the design aspects of a CMOS two-stage op-amp, focusing on bias currents, frequency compensation networks, degrees of freedom, constraints, and the sizing process with inequality constraints. It explores the relationships among DOFs and constraints to ensure proper circuit operation, emphasizing the importance of independent DOFs and valid solutions within specified regions.
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The simplest CMOS two-stage op-amp Bias currents of the op-amp = = 7 6 I I I I 0 1 bias bias 8 8 CC, RC: frequency compensation network First stage: p-input differential amplifier with mirror load Second stage: n-input common source class-A stage The input of the second stage is "referred to gnd" The output of the first stage is "referred to gnd" P. Bruschi Design of Mixed Signal Circuits 1
Use of a single M8 device to bias multiple op-amp M8 can be shared among different amplifiers and is not part of the op- amp architecture For this reason, we do not consider M8 in the amplifier topology P. Bruschi Microelectronic System Design 2
Degrees Of Freedom (DOFs) Possible DOFs: W, L of all devices (14 DOFs) I0, I1 CC, RC First estimate: Total number of DOFS: 18 But ... Not all DOFs are independent. It is necessary to choose a set of independent DOFs P. Bruschi Microelectronic System Design 3
Constraints Constraints are relationships among DOFs Two types of constraints: Equality constraints: I I Inequality constraints: = E.g. 6 1 0 7 ( ) GBW DOFs GBW E.g. min P. Bruschi Microelectronic System Design 4
Constraints Every equality constraint reduces the dimension of the DOF space. Equality constraints represent exact conditions that has to be fulfilled in order to guarantee correct operation of the circuit. Some equality constraints derive from simple considerations, such as symmetry: M1=M2, M3=M4. With a few exceptions, equality constraints are specific of the topology and does not depend on the specifications Inequality constraints are derived from the circuit specifications. They do not reduce the dimension of the DOF space but select regions of the DOF space where the specs are met. P. Bruschi Microelectronic System Design 5
The sizing process: role of multiple inequality constraints A very simple case with only two independent DOFs and two inequality constraints Combining the various inequality constraints, we find a domain (the intersection of all regions) where all points satisfy all constraints. All points in the domain are valid solutions. If such region does not exist (null intersection), the sizing problem is: "unfeasible". P. Bruschi Microelectronic System Design 6
The sizing process: automatic algorithms Computer programs that perform automatic sizing, are not compatible with an infinite number of feasible solutions. To find a single solution, an optimization condition is often added. If the design is performed manually, any point (set of DOFs values) in the intersection domain is a good solution. Also in this case, optimization or arbitrary techniques can be used to operate the choice P. Bruschi Microelectronic System Design 7
Sizing of a new topology: steps 1. Find equality constraints to reduce the number of independent DOFs. These constraints will be of two types: (a) Strictly necessary constraints (if not respected the circuit does not work properly) (b) Arbitrary constraints: they are added to further reduce the DOF set and simplify the design. These constraints should be motivated. 2. Choose a set of DOFs that have the following properties: (a) the remaining dependent DOFs can be easily derived from this set; (b) the specifications (inequality constraints) can be written easily and in a simple form as a function of the selected DOFs 3. Write the specifications in terms of the selected DOFs and try to find general design rules. P. Bruschi Microelectronic System Design 8
Equality constraints for the simple 2-stage op-amp Symmetry (necessary to obtain low offset and low CMRR N. of equality constraints M1=M2 (W1=W2, L1=L2) ------ 2 M3=M4 (W3=W4, L3=L4) ------ 2 Current ratios I I / / W W L L = = 6 6 6 1 -------------- 1 0 7 7 7 Initial DOF number: 18 , Resulting DOFs after reduction: 18-5=13 P. Bruschi Microelectronic System Design 9
Necessary constraint: null systematic offset It is not possible to exactly predict Vout, but it will be far from Vdd/ 2 if ISCis consistently different from zero P. Bruschi Microelectronic System Design 10
Necessary constraint: null systematic offset = = = I I 0 I I I 6 5 D D 6 5 SC D D = 6 D I I 6 0 7 Since only a common mode voltage is applied to the input: = = V V V V 5 3 H K GS GS I = = 0 I I 3 4 D D 2 I I 1 2 = 0 5 I = = I I 0 5 6 = I 5 6 5 D 2 5 6 D D 0 2 3 3 7 3 7 P. Bruschi Microelectronic System Design 11
More constraints 1 2 = 5 6 Null (small) systematic offset 3 7 Arbitrary constraints Good matching M5-M3: L5=L3 Good matching M6-M7: L6=L7 V V Symmetric output swing (same margins to Vdd and gnd) )5 GS t V V GS t 6 Let's now consider the output characteristic ( )5 V V ( = V V GS t GS t 6 P. Bruschi Microelectronic System Design 12
Residual number of DOFs 13 - 4 = 9 Of these residual DOFs we can separate two ones (CCand RC) that do not affect the dc performances and the operating point. We will come back to them later. Then we will focus on 7 DOFs (bias current I0and device size) that affect the operating point and we will call them "static" DOFs). We could select 7 DOFs within the original set (16 DOFs, RCand CCare not included) and then try to derive the remaining ones using the equations that tie them (equality constraints). It is more useful to choose a set of DOFs that may not necessarily include the original 18, in a way that the other ones can be easily derived. P. Bruschi Microelectronic System Design 13
Selection of the 7 DOFs Rationale: the most important MOSFETs of the circuits are M1 (=M2) and M5, since these are the devices that are at the heart of the two stages, where they perform the V-to-I conversion. We include all possible DOFs of M1 and M5 into the selected set M1: , , W L V V 1 1 GS V t 6 DOFs 1 M5: , , ( ) W L V 5 5 5 GS t To complete the set, let us include also L6into the DOFs Final set of static DOFs: 1 1 , , GS W L V , , , ( ) , V W L V V L 5 5 5 6 t GS t 1 P. Bruschi Microelectronic System Design 14
Derivation of all the op-amp parameters from the 7 DOFs All conditions will refer to the operating point (Vid=0) M2 is dentical to M1, then M1 DOFs specify also M2 parameters 0 1 1 5 2 , D D I I I = = = = I C W L ( ) 2 p OX ( , , ) I f W L V V V V 1 1 1 1 D p GS t GS t 1 1 2 1 W L C ( ) ( ) 2 W L = = , , 5 n OX I f V V V V 5 5 5 D n GS t GS t 5 5 2 = 5 M3=M4: L L 3 5 = D I ( V I C W L I W L 3 1 D = 3 3 3 n OX D ) ( ) ( ) 2 2 = V V V V V , W L 3 3 GS t GS t GS t 3 5 3 3 3 P. Bruschi Microelectronic System Design 15
Derivation of all the op-amp parameters from the 7 DOFs M6: = D I I 6 5 D 6 L ( )5 = V V V V GS t GS t 6 C W L I W L p OX , = W L 6 6 6 D 6 6 ( ) 2 2 V V 6 6 GS t 6 = L L 7 6 M7: D I V = 2D I V W L 7 7 1 , W L = V V 7 7 7 GS t G S t 7 6 P. Bruschi Microelectronic System Design 16
Small-signal equivalent circuit (-) (+) = = = R R r r r r r r = G g 1 4 2 1 3 d d d d 1 1 m m = G g 2 5 m m 2 5 6 d d Note: the equivalent circuit can be used to represent the behavior of most two-stage topologies, not just the simple amplifier of the figure. = + + C C C C 1 2 + 4 5 DB DB GS = 2' C C C All these values are functions of the DOFs 2 L = + 2' C C C 5 6 DB DB P. Bruschi Microelectronic System Design 17
dc gain = v G v R 1 1 1 m id G v R = v 2 1 2 out m ( ) = G v = = v G R R G RG R v A G RG R 2 1 1 2 out m m id 1 1 2 2 m m id 0 1 1 2 2 m m P. Bruschi Microelectronic System Design 18
dc gain as a function of the DOFs = G g = A G RG R 1 1 m m 0 1 1 2 2 m m = G g 2 = = 5 m m 1 1 = A g g = R R r r r r r r 1 r 1 1 1 0 1 5 m m 1 4 2 1 3 d d d d + + r r r 2 5 6 d d I 1 1 3 5 6 d d d d = g D = = I I I I m V 1 3 D D 1 TEV V 1 + 1 + TE = A 1 r ( )( ) 5 6 D D 0 = = g I d D 1 5 1 3 5 6 TE d P. Bruschi Microelectronic System Design 19
Frequency response of a two-stage op-amp This circuit does not include all components that affect the frequency response: P. Bruschi Microelectronic System Design 20
First stage c Frequency response 1 gs C = id 2 Ctail The short circuit output current of the first stage also depends on frequency I0 M7 Tail pole Vi2 Vi1 V M1 M2 out (+) ( ) V1 K H M3 M4 The tail pole and mirror pole (and a zero created by their combination) affect Ym(s). Frequencies are of the order of Mirror pole Cmirror These capacitances determine the load presented by the amplifier to the signal source. We will suppose that vi1and vi2are produced by ideal voltage sources, thus no loading effect will be considered 1 g C : m f 2 p P. Bruschi Microelectronic System Design 21
Frequency response, simplified small-signal circuit If the compensation group CC-RCis not present: We still have Cgd5 parasitic capacitance, which is not sufficient to produce the compensation effect P. Bruschi Microelectronic System Design 22
Uncompensated frequency response 1 g C g C = , d m f f Cgd5-Miller 1 2 p p C r p d p p , R R r fp1 fp2 1 2 C d ( , , .) C C C parasitic cap 1 2 5 gd p Without compensation, we have two poles at frequencies fp1, fp2, which are of the same order of magnitude and none of them is dominant. The result is a very small or even negative (= instability) phase margin. P. Bruschi Microelectronic System Design 23
Miller compensation = Pole splitting It is convenient to divide the bridge impedance RC-CCinto two impedances by means of the Miller theorem To do this, we need to calculate the Miller factor K=vout/v1. We force voltage v1and use the Norton equivalent model of the output port. sC sC R v = = C v G out sc i G v 1 1 2 m + 1 2 1 m 1 + R C C C sC C + G sC R G sC R + sC = iout-sc 2 2 m C C m C v 1 1 C C P. Bruschi Microelectronic System Design 24
Miller factor + G sC R G sC R + sC = 2 2 m C C m C out sc i v 1 1 iout-sc C C 1 C + 1 sC R + 1 sC R sG C C C G C C = 2 m vG = 2 m out sc i vG 1 2 m + 1 sC R 1 2 m + 1 sC R C C C C 1 + 1 sC R C C G = = 2 m ( ) ( ) v Z s i Z s vG out sc 1 2 out m + 1 sC R C C v Z(s) = ( ) out v K s Miller factor: 1 P. Bruschi Microelectronic System Design 25
Transformation of the bridge impedance ZCby the Miller Theorem 1 + 1 sC R C C G v = = Z 2 m out v K ZG 2 m + 1 sC R 1 C C ( ) ( ) = = 0 Z f R The low frequency limit of the K factor: 0 K f G R 2 2 2 m Z 1 (1 = = C K Z Z 1 M j C ) 1 K C C K 1 1 KZ = = = Z f C Z j C C 2 M C R j C (1 ) K 2 1 K C C C C P. Bruschi Microelectronic System Design 26
Miller transformations: shifting the input pole to very low frequencies 1 (1 Z KZ K = = C K Z = = C Z 1 M j C 1 ) K 2 M j C 1 (1 ) K K C Using C = = (0) K K G R 2 2 m 1 + 1 1 = Z Z 1 M j C j C G R 2 M (1 ) j C G R 2 2 2 2 C m C m C This sets the dominant pole: 1 First effect of Miller compensation: a very large capacitor Gm2R2CCis brought back to the input mesh, shifting the input pole back to low frequencies: p R G R C 1 2 2 m C P. Bruschi Microelectronic System Design 27
Second effect of Pole Splitting: shifting the output pole to high frequencies CC NO RC vout h o We cannot use the Miller theorem again, because the resulting pole would fall at frequencies where K is very different from K(0). v1 vi2 vid C2 R1 R2 C2M Gm1vid Gm2v1 C1 vi1 1 C 1 C 1 C R , R R and still: At frequencies such that: C 2 1 C 2 1 The equivalent circuit reduces to: Current source Gm2v1is controlled by the voltage across it: C + = C v v 1 out C C 1 C P. Bruschi Microelectronic System Design 28
Second effect of Miller Compensation: shifting the output pole to high frequencies v = out i R Then, it is equivalent to a resistance: V C + C + = C v G = = C v v i G v 2 out m 1 out 2 1 m C C C C 1 C 1 C + 1 v C C C C C = = = + This resistance "sees" a capacitance: 1 1 + out i C C C R C C 2 V V G C 2 1 m C C 1 = This sets a pole at: Note: Rvis actually the op-amp output resistance at medium and high frequencies. It is of the order of 1/Gm2 and is much smaller than the value in dc (order of rd). 2 R C V V 1 = 2 + 1 C C C C C + C 1 1 + C C C 2 G C 2 1 m C C P. Bruschi Microelectronic System Design 29
Second effect of Miller Compensation: shifting the output pole to high frequencies G C C 1 1 = 2 m = = + + C C C C 2 + R C 1 C C C C C 1 2 2 1 C C C + V V C 1 1 + C C C 2 G C C 2 1 m C C G G = = C C C 2 m 2 1 C m Series of C1 and C2 = C 1 + 2 2 C C C C C C ( ) S + + C + + C C 1 2 1 C C 1 + 2 1 2 2 1 1 2 C C 1 2 C G = 2 m 2 C C ( ) + + 1 C C S 1 2 C P. Bruschi Microelectronic System Design 30
Miller Factor and overall transfer function 1 + 1 sC R C C G v = = 2 m Miller factor: ( ) out v K s ZG 2 m + 1 sC R 1 C C v v v v v v = = = ( ) out v out v A K s 1 1 Factorizing A: 1 id id id P. Bruschi Microelectronic System Design 31
The zero introduced by RC-CC 1 + 1 sC R v v v v v v C C G v = = = ( ) out v out v A K s 1 1 = = 2 m ( ) out v K s ZG 2 m + 1 sC R 1 id id id 1 C C 1 G C If RC=0 (no RC) There is a zero in K(s): = = 0 2 m s z 1 1 C C = s C G z 1 2 m C R C C G This zero occurs also in the overall transfer- function of the amplifier (A). It cannot be cancelled by an equal zero, since an unstable pole (>0) would be required 2 m P. Bruschi Microelectronic System Design 32
Effects of the zero in the transfer function Thanks to RC: R = 0 1 C = s G C z 1 = 0 2 m s C R z C C G C 2 m 1 zs = R C G 2 m With this choice for RC, we can eliminate the zero and cancel its bad effect on the phase delay. Other possible choices are possible: for Rc>1/Gm2it is possible to change the positive zero into a negative one and use it to compensate fp2. Degradation of the phase margin P. Bruschi Microelectronic System Design 33
Summary of pole splitting Capacitor CCintroduces a feedback across the second stage that: 1. Puts an equivalent large capacitor (CCGm2R2>>C1) across the output resistance of the first stage (R1) shifting the first pole back to very low frequencies 2. Reduces the output resistance (RV) at medium/high frequencies from R2to a value close to 1/Gm2. This shifts the output pole to much higher frequencies. 3. Resistor RCis significant only at high frequencies and "shapes" the zero, either cancelling it or turning it into a negative zero P. Bruschi Microelectronic System Design 34
Pole splitting, graphical view After compensation Before compensation P. Bruschi Microelectronic System Design 35
Summary of singularities 1 = s 1 z 1 p C R RG R C C C G 1 2 2 m C 1 2 m G G C C C C C = + 1 2 2 C m m S = C 1 + 2 ( ) 2 + C S C C C ( ) + + 1 2 C 1 C C S 1 2 1 2 C This third pole (s3= 3), can be guessed considering that at very high frequencies the whole network reduces to the three capacitors and resistor RC. 1 3 2 1 1 C 1 1 + + R C C C 1 2 C P. Bruschi Microelectronic System Design 36
