Detecting Recycled ICs using Two-Pattern IDDQ Test
Explore the innovative Two-Pattern IDDQ Test for detecting recycled ICs without hardware modifications or golden samples. Understand the impact of aging on IDDQ, process variation, and non-uniform aging in circuits. Discover a method to identify recycled ICs efficiently.
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Two-Pattern IDDQTest for Recycled IC Detection Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal Dept. of Electrical and Computer Engineering, Auburn University, Auburn, AL-36849, USA
Outline Motivation and contributions IDDQ modeling in gates Aging and its effect Process variation Non-uniform aging in circuit Proposed method to detect recycled IC Simulation results and discussion Conclusion 2
Motivation and Contribution Recycled ICs used ICs represented as new are a well recognized problem in today s global component supply chain. A method for detecting recycled ICs. No hardware modification required to the existing design. No golden samples required. Can identify devices used as little as six months. 3
Aging and its effect on IDDQ Negative Bias Temperature Instability (NBTI) is a major aging phenomenon, which occurs in PMOS devices. Aging in NMOS devices is significantly lower. Due to NBTI aging PMOS threshold voltage (vth) increases. Increased vth increases leakage resistance (RP) of a PMOS device. 4
IDDQ Modeling in CMOS Gates VDD AB=01 VDD AB=00 Pattern AB=11 controls age dependent IDDQ of NAND gate. RP RP RP RP RN RN VDD IDDQ= VDD/2RN IDDQ= VDD/RN RN RN PN GND GND M1 M2 VDD AB=11 VDD AB=10 Y RP RP RP RP M3 A RN RN M4 B NN IDDQ= VDD/RN IDDQ= 2VDD/ RP RN RN GND GND GND (a) NAND Gate (b) IDDQ Model 5
IDDQ Modeling in CMOS Gates - Cont. Inputs NAND NOR Inverter A B IDDQ(A) V/2RN V/RN V/RN 2V/RP IDDQ(U) IN/2 IN IN 2IP IDDQ(A) 2V/RN V/RP V/RP V/2RP IDDQ(U) 2IN IP IP IP/2 IDDQ(A) V/RN NA IDDQ(U) IN NA 0 0 0 1 1 0 NA NA 1 1 V/RP IP IDDQ(A) = Absolute IDDQ current IDDQ(U) = IDDQ current in terms of IN and IP where IN= V/RN and IP= V/RP 6
Non-uniform Aging of gates on a Chip PMOS devices of gates 4 and 5 (red) age faster and those of gates 6 and 7 (blue) age slower. Pattern T1 controls IDDQ through fast aged gates and pattern T2 controls IDDQ though slow aged gates. p1=0.5 G1 a1 a2 a3 a4 a5 a6 a5 a6 [1,0] a1 p7 = 0.75 [0,1] T2 0 0 1 1 1 1 T1 1 1 0 0 0 0 G6 o1 p2 = 0.5 a2 p10= 0.875 G4 [0,1] p3= 0.5 p4 = 0.5 a3 a4 p8 = 0.25 [1,0] G2 p11= 0.9375 G7 o2 p5 = 0.5 p6 = 0.5 p9 = 0.25 G5 G3 [0,1] 7
Process variations Process variation causes variations in threshold voltages of MOS devices. Random variation affects vth of MOSFETs within a chip. Systematic variation affects vth of MOSFETs on different chips. These variations create inaccuracy in IDDQ- based aging decision. 8
Process Variation Resilience IDDQ for T1 and T2 : ?+ ?1 ?? ?+ ?2 ?? ?1= ?1 ?? ?2= ?2 ?? k1 and k2 = Number of PMOS OFF when T1 and T2 applied r1 and r2 = Number of NMOS OFF when T1 and T2 applied The difference, I2 I1: ? ?1 ?? ?+ (?2 ?1) ?? ????= ?2 ?? ????= ??+ ?? 9
Process Variation Resilience Cont. ? ?1 ?? ? ??= ?2 ?? ??= (?2 ?1) ?? IP is contributed by PMOS and IN is contributed by NMOS Select T1 and T2 such that r1 r2 to eliminate process variation in NMOS devices. Effect of random process variation is nullified when #gates is large. 10
Process Variation Resilience Cont. Normalization of IDDQ removes systematic process variation. A normalized value used for recycled IC detection: ? =?2 ?1 ?2+?1 100% 11
Simulation Results ISCAS benchmarks c432, c499, c880, c1908 and c3540 simulated. Synthesis is done in Synopsys design compiler and HSPICE netlist created using IC validator. Synopsys VCS provided controllability analysis CMOS 32nm Predictive Technology Model (PTM) Aging simulations at 25 degree Celsius and 1V 12
IDDQ for new Circuits Benchmark Netlist-1 I% Netlist-2 I% Netlist-3 I% Netlist-4 I% IT % max( I%) c432 3.65 3.65 3.5 3.80 3.80 c499 1.36 1.54 1.62 1.39 1.62 c880 4.26 4.46 4.65 4.58 4.65 c1908 2.14 2.38 2.76 2.94 2.94 c3540 3.74 3.85 4.19 3.88 4.19 13
IDDQ for used circuits Usage Benchm ark c432 c499 c880 c1908 c3540 c432 c499 c880 c1908 c3540 Netlist-1 I% 5.16 3.26 5.26 4.35 4.86 5.37 3.59 5.44 4.58 5.03 Netlist-2 I% 5.09 3.51 5.45 4.58 4.91 5.33 3.80 5.62 4.83 5.07 Netlist-3 I% 4.97 3.56 5.65 4.71 5.17 5.19 3.88 5.81 5.02 5.32 Netlist-4 I% 5.23 3.31 5.54 4.88 5.00 5.48 3.59 5.76 5.09 5.14 min ( I) % 4.97 3.26 5.26 4.35 4.86 5.19 3.59 5.44 4.58 5.03 6 months 12 months 14
Conclusion Two pattern test can effectively identify recycled ICs used for as little as six months The test requires no additional design change in the device Test can be applied by any available automatic test equipment (ATE) Finding optimal two pattern can be investigated further. 15
Thank you! Questions? 16
