Digitization System R&D for APV25 at China Institute of Atomic Energy
This project focuses on developing a system to control, digitize, and save the output of APV25, a 128-channel pre-amplification device with a single analogue differential output. It involves system construction, digital data processing, analogue data transmission, and utilization of components like FPGA, ADC, and PC. The mission is to advance research in the field of atomic energy through efficient data handling solutions.
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Presentation Transcript
Digitization System R&D for APV25 Xinglong Li China Institute of Atomic Energy ( )
Outline Introduction System construction Results Next step
Introduction -> APV25 128 channel pre-amplification 192 cell pipeline a single analogue differential output -> Objective Develop a system to control APV25 , digitize and save the APV25 output . -> Similar system existing SRS (scalable readout system) @RD51 -developed MPD (Multi Purpose Digitizer) @INFN - developed MRS (Multiple-chip Readout System) ... @USTC -developing MRS SRS MPD
Outline Introduction System construction Results Next step
System construction Digital data GbE Analogue data HDMI APV25 ADC FPGA PC Parameters Clock, Trigger, Cmd HDMI Spartan 6 GbE power ADS5242 power APV25 backplane
APV25 details Digital data GbE Analogue data HDMI APV25 ADC FPGA PC Clock, Trigger, Cmd Parameters Clock Trigger Command(I2C) Channel 1 2 3 Analogue data Preamplifier Preamplifier Preamplifier Shaper Shaper Shaper Buffer Buffer Buffer APSP APSP APSP 128:1 Multiplexer . . . . . . . . . . . . . . 128 Preamplifier Shaper Buffer APSP
ADC details Digital data GbE Analogue data HDMI APV25 ADC FPGA PC Clock, Trigger, Cmd Parameters Clock Command Analogue data ADS5242 4-Channel 12-Bit 65MSPS Serial digital data Analog-to-Digital Converter
FPGA details Digital data GbE Analogue data HDMI APV25 ADC FPGA PC Clock, Trigger, Cmd Parameters ISERDES2 Serial to parallel FIFO Serial digital data Gigabit Ethernet cable Clock GbE MAC (UDP) To ADC & APV25 RTL8211E PHY I2C ADC Ctrl Spartan 6 FPGA utilization: 50% BUFG, 22% IO, 10% others
PC details Digital data GbE Analogue data HDMI APV25 ADC FPGA PC Clock, Trigger, Cmd Parameters LabVIEW program UDP send Datagram to data Waveform UDP receive GbE cable C program based on SOCKET API SOCKET sendto binary file SOCKET recvfrom
Outline Introduction System construction Results Next step
APV25 data received (LabVIEW) header, addr, error ticks Signal injected Signal of 1~128 channel Jones, L. L., et al. "The APV25 deep submicron readout chip for CMS detectors." (1999).
Gigabit Ethernet speed test(SOCKET) -> UDP protocol with Cumulative acknowledgment (1 ACK every 10 datagram) -> 731 second, 108datagrams, no lost, 40GB file (on SSD) , i.e. 460Mb/s -> Time cost: Send ACK 14% Receive datagram 62% Write to file 24% The UDP function of LabVIEW is slower
Outline Introduction System construction Results Next step
Next step FPGA Add zero compression to reduce data rates to the computer. Add Retransmission timeout to make the transmission more reliable. LabVIEW program Use SOCKET API or other similar API instead of the slow UDP function. Improve data processing and save the results. New version system Design FPGA board instead of the development board. Digitize 8 or 16 APV25 in 1 system.
