DisplayPort Bandwidth Considerations for Efficient Video Data Transport

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Explore the factors that determine the number of lanes and data rate required to transport video data over DisplayPort main link efficiently, considering resolutions, refresh rates, bit-per-color, and more.

  • Bandwidth
  • Video Transport
  • DisplayPort
  • Resolution
  • Data Rate

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  1. Link Bandwidth Consideration (1/8) The number of xcvr lanes and data rate required to transport the video data across the DisplayPort main link depends on the following factor: Resolution of the image Refresh rate Bit-per-color Number of video stream (for Multi-stream Transport) The video stream clock frequency (tx_vid_clk or rx_vid_clk) must be higher than the link symbol clock frequency (tx_ss_clk or rx_ss_clk) to prevent link bandwidth oversubscription The following examples determines: The number of lanes required The data rate The minimum video stream clock (pixel clock) frequency Symbol/clock and pixel/clock settings of the DisplayPort IP core Intel Confidential Programmable Solutions Group 2

  2. Link Bandwidth Consideration (2/8) The resolutions of the image are standardized by various video timing standard defined by VESA (CVT) & CEA Source: Wikipedia Intel Confidential Programmable Solutions Group 3

  3. Link Bandwidth Consideration (3/8) Display resolution consists of the number of pixels in active video and blanking period Video & Image Processing Suite User Guide v16.0 Intel Confidential Programmable Solutions Group 4

  4. Link Bandwidth Consideration (4/8) Single Stream Transport Example: Video active resolution = 1920 x 1080 pixels Horizontal blanking (H blanking) = 280 pixels Vertical blanking (V blanking) = 45 pixels Refresh rate = 60Hz/frame Bit-per-color (bpc) = 8 bit-per-pixel = 8 x 3 = 24 (3 colors: red, green, blue) Standard blanking ANSI/CEA Standard CEA-861-F Intel Confidential Programmable Solutions Group 5

  5. Link Bandwidth Consideration (5/8) Single Stream Transport Example: Total horizontal pixel (H total) = H active + H blanking Total vertical pixel (V total) = V active + V blanking Total pixels per frame per second = H total x V total x refresh rate = 2200 x 1125 x 60 = 148,500,000 pixels/s Total bits per frame per second = total pixels per frame per second x bit-per-pixel = 148,500,000 x 24 = 3,564,000,000 bits/s = 3.564Gbps With 8b/10b encoding/decoding overhead, total bits/s across main link = 3.564 x 10/8 = 4.455Gbps = 1920 + 280 = 2200 pixels = 1080 + 45 = 1125 pixels Intel Confidential Programmable Solutions Group 6

  6. Link Bandwidth Consideration (6/8) Single Stream Transport Example: The total bandwidth of xcvr lanes required MUST be equal or higher total of bits/s across the link. Possible main link configuration: 4 x 1.62Gbps (RBR) = 6.48Gbps 2 x 2.7Gbps (HBR) = 5.4Gbps 1 x 5.4Gbps (HBR2) The stream clock frequency (f_strm_clk) = 148.5MHz The minimal local pixel clock frequency (f_vid_clk) = f_strm_clk/pixels_per_clock Pixels_per_clock = Pixel input/output mode setting (1, 2, 4) If f_vid_clk frequency is higher (e.g. 160MHz) than 148.5MHz, the video data valid signal is de- asserted when there is no active video in the stream Refer to next slide for timing diagram If f_vid_clk is the same as 148.5MHz, the video data valid signal is asserted in every clock cycle Link to Video PLL slide Intel Confidential Programmable Solutions Group 7

  7. Link Bandwidth Consideration (7/8) The CVI IP cores only read the vid_data, vid_de, vid_h_sync, vid_v_sync, and vid_f signals when vid_datavalid is 1. This allows the CVI IP cores to support oversampling where the video clock is running at a higher rate than the pixel clock Video & Image Processing Suite User Guide v16.0 Intel Confidential Programmable Solutions Group 8

  8. Link Bandwidth Consideration (8/8) Multi-Stream Transport Example Number of stream = 4 Video stream details Resolution of each stream = 1920 x 1080 Refresh rate of each stream = 60Hz Bit-per-color of each stream = 10 (30-bit per pixel) Total bits per frame per second with 8b/10b encoding overhead = 148,500,000 x 30 x 4 x 10/8 = 22,275,000,000 = 22.275Gbps Data rate per lane = 22.275/4 = 5.56875Gbps > 5.4Gbps Options to overcome bandwidth limitation: Reduce refresh rate to 30Hz Data rate/lane = 2.784375Gbps Reduce bit-per-color to 8 bpc Data rate/lane = 17.82Gbps/4 = 4.455Gbps Use reduce blanking (CVT-R) with the same resolution Reduce the resolution Not supported! Intel Confidential Programmable Solutions Group 9

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