Effect of Layout Design on Clocking Frequency
Explore the impact of trace layouts on clocking frequency in circuit design, with insights on optimizing layout for maximum performance. Results show the influence of different trace configurations on clocking frequency. Conclusions highlight the importance of layout choices in minimizing clock frequency reduction and maximizing performance.
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Presentation Transcript
Layout Design and the Effect on Maximum Clocking Frequency By: Jay McDaniel
Project Description Goals Determine how trace layouts effect propagation delay and maximum clocking frequency Create a lab that could be used for future students Deliverables Design, build, and test circuit used for lab Lab write-up that includes background information, pre-lab, procedure, and questions
ADS Results Using D-Type Positive Edge Triggered D Flip Flops with a tp= 16.5ns and ts= 6.5ns (NC7SV74K8X) Tmin = 16.5ns + 6.5ns + 1.433ns = 21.433ns => fmax=46.65MHz (straight and curved corner) Tmin= 16.5ns + 6.5ns + 1.533ns = 21.533ns => fmax= 46.44MHz (90ocorner trace) Leads to a 210KHz slower maximum clocking frequency
Simulation Results Straight Trace: fmax= 46.47MHz => tmin= 21.52ns Curved Trace: fmax= 46.45MHz => tmin= 21.53ns 90oTrace: fmax= 46.16MHz => tmin= 21.66ns (Note: fmaxis 310KHz slower than that for straight trace) Using straight trace as my control, I found D = .152ns/in (90otrace effective length equal to 10.92 )
Conclusions Trace layout should either be laid out in a straight fashion or using curved corners to minimize clock frequency reduction 90otraces can effectively add length to your trace length which in turn adds more delay and reduces your maximum clocking frequency 90ocorner traces should be avoided at all cost but probably inevitable due to vias
