Efficient 1TnR-Based ReRAM Crossbar Memory
Explore the construction of a fast and energy-efficient 1TnR-based ReRAM crossbar memory for main memory, overcoming challenges and highlighting the benefits of ReRAM technology. Discover the structure, design, and experiments associated with V-ReRAM design and location-aware RESET. Dive into the details of ReRAM cell operations, crossbar structure, and sneak path challenges. Learn about the unique features of ReRAM compared to traditional memory technologies, emphasizing better scalability, higher density, endurance, and non-volatility.
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Presentation Transcript
Constructing Fast and Energy Efficient 1TnR based ReRAM Crossbar Memory Lei Zhao1, Lei Jiang2, Youtao Zhang1, Nong Xiao3, Jun Yang1 1 University of Pittsburgh 2 Indiana University Bloomington 3 National University of Defense Technology
ReRAM for Main Memory Overcoming the Challenges of Crossbar Resistive Memory Architectures [Xu et al. HPCA 15] Understanding The Trade-Offs In Multi-Level Cell ReRAM Memory Design [Xu et al. DAC 13] Design of Cross-point Metal-oxide ReRAM Emphasizing Reliability and Cost [Niu et al. ICCAD 13]
Highlight of ReRAM Better scalability Scaling path of DRAM beyond 16 nm is unclear Higher density 4F2 cell size for cross-point ReRAM (6F2 for DRAM) Higher endurance ReRAM has superior endurance (1010) than PCM (107) Non-volatility
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
ReRAM Cell LRS ( 1 ) HRS ( 0 ) Oxygen Ion - + RESET Electrode Oxygen Vacancy Metal Oxide Electrode SET - + Cell Operations Cell Structure
Crossbar Structure & Sneak Path Sneak current causes voltage drop on target cell Voltage drop degrades performance and increases energy consumption ? 2 ? 2 ? 2 0 V ? 2 ? 2 ? 2 Half Selected Cell Word LineBit Line Cell
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
1T4R BL0 BL1 BL2 BL3 WL0 WL1 BL0BL1 BL2BL3 WL2 GWL0 WL3 Write Driver GWL1 GWL0 GSL0 GSL1 GWL1 SA GSL0 GSL1 [Yeh et al., JSSC 15]
Double-Sided Ground Biasing Worst Case Cell Worst Case Cell Write Driver Write Driver [Xu et al., HPCA 15] SA We employ DSGB in both baseline and out design schemes
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
Motivation ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 0 0 Reset N (=2) cells V ? 2 6 half selected cells on WLs Write Driver Write Driver ? 2 N x (512-1) half selected cells on BLs 6 + 2 x (512-1) = 1028 total half selected cells V V SA
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
V-ReRAM Re-allocate write drivers and sense amplifier Write Driver Write Driver Reset N (=2) cells N x 3 half selected cells on WLs SA 512 - N half selected cells on NWLs 2 x 3 + 512 2 = 516 total half selected cells
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
RESET Variation block0 Write Driver block1 90 80 RESET Latency (ns) 70 60 SA 50 40 block30 30 block31 20 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Block ID Write Driver block62 block63
Location-aware RESET Terminate RESET phase early Use a timing table in memory controller 16 entries Entry i stores RESET latency for block 2i, 2i+1, 64- 2i, and 64-(2i+1) Each entry uses 2 Bytes, 32 Bytes in total
Outline Background 1TnR ReRAM Structure Motivation & Goals V-ReRAM Design Location-aware RESET Experiments
Evaluation Setup Device Simulation HSPICE & Stanford-PKU RRAM Model In-house cycle accurate simulator 8 cores CMP Private L1 & L2 caches 8GB, 1 channel - 2 rank - 8 bank, ReRAM Main Memory Schemes Baseline: 1T4R cross-point with DSGB V-ReRAM: Re-allocated peripheral circuit V-ReRAM-Var: Location-aware RESET early termination Benchmarks SPEC CPU 2006 (both write intensive and non-intensive)
Performance V-ReRAM and V-ReRAM-Var reduces RESET latency by 6% and 23% on average 1.2 Baseline V-ReRAM V-ReRAM-Var 1.1 7.2% Normalized IPC 1.5% 1 0.9 0.8 gro zeu wrf cac mcf lbm ast sop Gmean
Energy Not only reduces # of half selected cells, but also reduces # of activated WLs 0.5 V-ReRAM V-NUMA 0.4 Normalized Energy 28% 0.3 0.2 0.1 0 gro zeu wrf cac mcf lbm ast sop Amean
Sensitivity Study More performance and energy benefits for larger subarrays Tolerate subarrays that can provide more bits in an access Varying Subarray Size Varying Subarray Width V-ReRAM IPC V-ReRAM-Var IPC V-ReRAM IPC V-ReRAM-Var IPC V-ReRAM Energy V-ReRAM-Var Energy V-ReRAM Energy V-ReRAM-Var Energy 1.3 0.6 1.3 0.6 Normalized Energy Normalized Energy 0.5 5.3 0.5 1.2 Normalized IPC 1.2 Normalized IPC 0.4 0.4 1.1 1.1 0.3 0.3 1 1 0.2 0.2 0.9 0.9 0.1 0.1 0.8 0 0.8 0 256x256 512x512 1024x1024 8 cells 16 cells 32 cells
Conclusion Based the state-of-the-art schemes to further reduce RESET leakage Reduce the # of total half selected cells by re- allocating peripheral circuits Exploit RESET latency non-uniformity to terminate fast RESET early Achieves 7.2% performance boost and 28% energy saving
Thank You & Questions
