Efficient Synchronization Support for Near-Data-Processing Architectures
Synchronization challenges in near-data-processing systems are addressed by SynCron, providing an end-to-end solution for efficient synchronization in NDP architectures, improving performance and energy utilization. The solution involves shared memory, hardware cache coherence, software-based schemes, and specialized hardware support.
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SynCron Efficient Synchronization Support for Near-Data-Processing Architectures Christina Giannoula Nandita Vijaykumar, Nikela Papadopoulou, Vasileios Karakostas Ivan Fernandez, Juan G mez Luna, Lois Orosa Nectarios Koziris, Georgios Goumas, Onur Mutlu
Executive Summary Problem: Synchronization support is challenging for NDP systems Prior schemes are not suitable or efficient for NDP systems Contribution: SynCron: the first end-to-end synchronization solution for NDP architectures Key Results: SynCron comes within 9.5% and 6.2% of performance and energy of an Ideal zero-overhead synchronization scheme 2
Near-Data-Processing (NDP) Systems NDP Logic CPU Recommendation Systems Graph Analytics Neural Networks Bioinformatics 3
Synchronization is Necessary Image Processing Bioinformatics Graph Analytics Databases Single Source Shortest Path (SSSP) Barriers Locks for v in Graph: for u in neighbors[v]: if distance[v] + edge_weight[v, u] < distance[u] if distance[v] + edge_weight[v, u] < distance[u] distance[u] = distance[v] + edge_weight[v, u] lock_release(u) Concurrent Data Structures lock_acquire(u) 4
Baseline NDP Architecture NDP System NDP Unit Programmable Core / Accelerator NDP Core Main Memory NDP Core Private Cache NDP Core Synchronization challenges in NDP systems: (1) Lack of hardware cache coherence support (2) Expensive communication across NDP units (3) Lack of a shared level of cache memory 5
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support 6
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support CPUs: Hierarchical CLH Locks [EuroPar 06] Cohort Locks [TOPC 15] Ticket Locks [TOCS 91] MPPs: QOLB [ASPLOS 89] Lack of hardware cache coherence support 7
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support CPUs: MiSAR [ISCA 15] LCU [MICRO 10] Glocks [IPDPS 11] GPUs: HQL [IPDPS 13] GPUs: Fermi GF100 [IEEE Micro 10] MPPs: SGI Origin [ISCA 97] Cray T3E [ASPLOS 96] CPUs: SSB [ISCA 07] Lock Cache [CASES 01] MPPs: Full/Empty Bits [ISCA 83] NDPs: Tesseract [ISCA 15] Expensive communication across NDP units 8
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support CPUs: SSB [ISCA 07] Lock Cache [CASES 01] BarrierFilter [MICRO 06] CPUs: MiSAR [ISCA 15] GPUs: HQL [IPDPS 13] NDPs: Tesseract [ISCA 15], Near-Data Processing for In-memory Analytics [PACT 15] Lack of a shared level of cache memory 9
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support Prior schemes are not suitable or efficient for NDP systems 10
NDP Synchronization Solution Space (2) Message-passing (1) Shared Memory Hardware Cache Coherence Software- based Schemes Specialized Hardware Support Remote Atomics Specialized Hardware Support NDPs: SynCron s Key Techniques: 1. Hardware support for synchronization acceleration 2. Direct buffering of synchronization variables 3. Hierarchical message-passing communication 4. Integrated hardware-only overflow management SynCron [HPCA 21] 11
1. Hardware Synchronization Support NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 ` ` ` ` ` ISA Main Memory Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Local lock acquire No Complex Cache Coherence Protocols No Expensive Atomic Operations Low Hardware Cost 12
2. Direct Buffering of Variables NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Address Synchronization Table Local Synchronization Processing Unit -- lock acquire -- Indexing Counters -- -- 13
2. Direct Buffering of Variables NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Address Synchronization Table Local Synchronization Processing Unit 0x33A9 lock acquire No Costly Memory Accesses Low Latency -- Indexing Counters -- -- 14
3. Hierarchical Communication NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory syncronVar NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 NDP Unit 2 NDP Unit 3 NDP Core 0 NDP Core 0 Main Memory Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 2 Synchronization Engine 3 15
3. Hierarchical Communication Local lock acquire NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory syncronVar NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Master NDP Unit 2 NDP Unit 3 NDP Core 0 NDP Core 0 Main Memory Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 2 Synchronization Engine 3 16
3. Hierarchical Communication Global lock acquire NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory syncronVar NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Master NDP Unit 2 NDP Unit 3 NDP Core 0 NDP Core 0 Main Memory Minimize Expensive Traffic Main Memory NDP Core 1 NDP Core 1 Synchronization Engine 2 Synchronization Engine 3 17
4. Integrated Overflow Management NDP Unit 0 NDP Unit 1 NDP Core 0 NDP Core 0 Main Memory Main Memory syncronVar NDP Core 1 NDP Core 1 Synchronization Engine 0 Synchronization Engine 1 Fully Occupied Master Address 0x33A9 0x2241 0x438C 0x6B4A Synchronization Table Low Performance Degradation High Programming Ease Synchronization Processing Unit Indexing Counters 18
SynCron The first end-to-end synchronization solution for NDP architectures SynCron s Benefits: 1. High System Performance 2. Low Hardware Cost 3. Programming Ease SynCron comes within 9.5% and 6.2% of performance and energy of Ideal zero-overhead synchronization 4. General Synchronization Support 19
SynCron Efficient Synchronization Support for Near-Data-Processing Architectures Christina Giannoula Nandita Vijaykumar, Nikela Papadopoulou, Vasileios Karakostas Ivan Fernandez, Juan G mez Luna, Lois Orosa Nectarios Koziris, Georgios Goumas, Onur Mutlu
