Efficient Timing Channel Protection for On-Chip Networks

Efficient Timing Channel Protection for On-Chip Networks
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On-Chip Networks (OCNs) are shared resources in future large-scale multi-cores, leading to multiple applications/virtual machines coexisting. This study delves into the issue of timing channels causing interference due to shared NoCs, with a focus on security assurance systems. The research highlights challenges, such as covert channels in high-assurance environments, using examples of corporate virtual machines on the cloud. Solutions are proposed to eliminate timing channels via shared on-chip networks while ensuring information security and low performance overhead.

  • On-Chip Networks
  • Timing Channels
  • Security Assurance
  • Virtual Machines
  • NoCs
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  1. Title Efficient Timing Channel Protection for On-Chip Networks Efficient Timing Channel Protection for On-Chip Networks Yao Wang and G. Edward Suh Cornell University

  2. Title Efficient Timing Channel Protection for On-Chip Networks On-Chip Networks are Shared Resources Future large-scale multi-cores will be shared among multiple applications / virtual machines Virtual Machine A Virtual Machine B NOCS 2012 2/21

  3. Title Efficient Timing Channel Protection for On-Chip Networks Problem: Timing Channels Shared NoC causes interference Network interference introduces timing channels Virtual Machine A Side channel Covert channel High assurance systems requires security guarantee Example: Corporate virtual machines on the cloud Virtual Machine B NOCS 2012 3/21

  4. Title Efficient Timing Channel Protection for On-Chip Networks RSA Example RSA : a public key cryptographic algorithm Prone to timing channel attacks key: 0110 RSA Attacker Core 0 Core 1 Core 2 MC 0 MC 1 MC 2 Crossbar NOCS 2012 4/21

  5. Title Efficient Timing Channel Protection for On-Chip Networks RSA Example RSA : a public key cryptographic algorithm Prone to timing channel attacks NOCS 2012 5/21

  6. Title Efficient Timing Channel Protection for On-Chip Networks Outline Objective: Eliminate timing channels through the shared on-chip networks Completely eliminate information leakage Low performance overhead Rest of the talk Potential approaches Our solution Evaluation Related work Conclusion NOCS 2012 6/21

  7. Title Efficient Timing Channel Protection for On-Chip Networks Use Quality-of-Service? QoS techniques provide performance isolation to different network flows QoS techniques are not enough for security A flow can use bandwidth beyond its allocation Bandwidth utilization reveals the flow demand Flow A Demand B Flow B Demand Flow A 1 2 BW utilization A 50% Bandwidth allocation A: 50% B: 50% 100% 100% 100% 100% 0% NOCS 2012 7/21

  8. Title Efficient Timing Channel Protection for On-Chip Networks Static Partitioning To eliminate timing channels, resource allocation cannot depend on run-time demands Static partitioning Spatial Network Partitioning (SNP) Temporal Network Partitioning (TNP) Cycle 0 Cycle 1 VM A VM A VM B VM B SNP TNP Completely eliminate the timing channels High performance overhead NOCS 2012 8/21

  9. Title Efficient Timing Channel Protection for On-Chip Networks One-Way Information Leak Protection Usually only one-way information protection is needed Multi-level security (MLS) model Business App (Bank Management) Corporate VM High-Security Domain Information flow Personal APP (Music Player) Regular VM Low-Security Domain PC In general Cloud Computing One-way protection is the key for efficient timing channel protection NOCS 2012 9/21

  10. Title Efficient Timing Channel Protection for On-Chip Networks Timing Channel through NoC 1 HS: High-Security Domain LS: Low-Security Domain LS throughput HS ---> LS 0 1 HS demand NOCS 2012 10/21

  11. Title Efficient Timing Channel Protection for On-Chip Networks Reversed Priority with Static Limits (RPSL) Reversed Priority Assign high priority to low-security domain The behavior (throughput, latency) of low-security domain is not affected by high-security domain Static Limits Low-security domain could initialize Denial-of-Service (DoS) attack Static limit controls the amount of traffic that low-security domain can send during a certain interval NOCS 2012 11/21

  12. Title Efficient Timing Channel Protection for On-Chip Networks Implementation: Avoid Interference Priority-based separable allocator Input arbiter & Output arbiter Static virtual channel allocation Avoid head-of-line blocking Low-security Domain Virtual Channels Input link 0 High-security Domain 1 Router 2 3 NOCS 2012 12/21

  13. Title Efficient Timing Channel Protection for On-Chip Networks Implementation: Avoid DoS Static limit control mechanism Counter & Control logic Low-security Domain Winning Request Priority- based Arbiter Requests High-security Domain Static limit Control Counter Input Arbiter Apply to both input and output arbiter NOCS 2012 13/21

  14. Title Efficient Timing Channel Protection for On-Chip Networks HS Benefits of One-Way Protection 1 2 LS HS Round-robin Allocator HS BW Total BW Utilization LS LS Time Temporal Network Partitioning HS HS BW Total BW Utilization LS LS Time RPSL HS HS BW Total BW Utilization LS LS Time NOCS 2012 14/21

  15. Title Efficient Timing Channel Protection for On-Chip Networks Experimental Setup Goals of experiments Timing channel protection DoS protection Performance overhead Darsim: cycle-level NoC simulator Comparison of three schemes Round-robin allocator (ISLIP) Temporal Network Partitioning (TNP) Reversed Priority with Static Limits (RPSL) NOCS 2012 15/21

  16. Title Efficient Timing Channel Protection for On-Chip Networks Timing Channel: No Protection Simple network HS Low-security Domain 1 2 3 4 High-security Domain LS Round-robin allocator NOCS 2012 16/21

  17. Title Efficient Timing Channel Protection for On-Chip Networks Timing Channel: Two-way Protection Simple network HS Low-security Domain 1 2 3 4 High-security Domain LS Temporal Network Partitioning 0.4/1.0 NOCS 2012 17/21

  18. Title Efficient Timing Channel Protection for On-Chip Networks Timing Channel: One-way Protection Simple network HS Low-security Domain 1 2 3 4 High-security Domain LS Reversed Priority with Static Limits (Static limit = 0.8) 1.0/1.0 NOCS 2012 18/21

  19. Title Efficient Timing Channel Protection for On-Chip Networks Performance HIGH Applications show bursty traffic LOW RPSL is efficient for bursty traffic NOCS 2012 19/21

  20. Title Efficient Timing Channel Protection for On-Chip Networks Related Work Side-channel protection Shared resources are prone to side-channel attacks, e.g. shared caches, branch prediction Cannot be applied to NoC QoS schemes Allows resource usage beyond allocation Insufficient to prevent timing channel attacks Composability Remove interference between applications for fast integration Require bi-directional non-interference, incur high performance overhead NOCS 2012 20/21

  21. Title Efficient Timing Channel Protection for On-Chip Networks Conclusion Shared on-chip networks introduce timing channels Prevent effective sharing of large-scale NoC in high assurance systems One-way timing channel protection is sufficient in many situations RPSL provides efficient one-way timing channel protection Incurs low performance overhead NOCS 2012 21/21

  22. Title Efficient Timing Channel Protection for On-Chip Networks Extend to Multiple Domains NOCS 2012 22

  23. Title Efficient Timing Channel Protection for On-Chip Networks Denial-of-Service Protection (RPSL) Simple network HS Low-security Domain 1 2 3 4 High-security Domain LS Static Limit on LS Static Limit on LS NOCS 2012 23

  24. Title Efficient Timing Channel Protection for On-Chip Networks Synthetic Traffic Patterns HIGH 6-by-6 mesh network Two security domains LOW Transpose traffic LS offered BW LS offered BW LS offered BW Round-robin Temporal Network Partitioning RPSL NOCS 2012 24

  25. Title Efficient Timing Channel Protection for On-Chip Networks Synthetic Traffic Patterns HIGH 6-by-6 mesh network Two security domains LOW Hotspot Traffic Round-robin Temporal Network Partitioning RPSL NOCS 2012 25

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