EIC-AncBRAIN: Slow Control & Communication Management System
This system, developed by a group of contributors, serves as a bridge between lpGBT and EIC-LASs, offering key features such as robust error handling, broadcast signal generation, and internal sub-module control. Learn about its architecture, documentation, and transaction format for efficient design and implementation.
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EIC-AncBRAIN: A Slow Control & Communication Management System of AncASIC Date: 01/21/2025 Contribution: Melo, Soumyajit Mandal, Prafull Purohit, Sergio Rescia, Nicholas St. John, Grzegorz W. Deptuch Arif Iqbal, Dominik Gorni, Syed Hassan, , Joao de
Outline Architecture of AncASIC Key Features of EIC-AncBrain Documentation for Design and Implementation Transaction Format and Register/Error Code Definition EIC-AncBrain Block Diagram AncASIC System-Level Design and Implementation Flow Implementation Plan 2
AncBrain - Motivation Number of elinks available on lpGBT not enough to drive multiple EIC-LASs To lower the number of tracks between lpGBT and EIC-LASs Needs control and communication mechanism between lpGBT and EIC-LAS hence the AncBrain acting as a bridge 3
Key Features of EIC-AncBrain The key functions are: Internal Sub-Module Control Communication Bridging Broadcast Signal Generation Robust Error Handling System Stability System flexibility and customization DC coupling with CML-like inter-chip TX-RX link Each E-link shares 3 signals: SC_In, SC_Out, Cl_In 4
Documentation for Design and Implementation The key functions are: System Overview Architecture Communication Protocols Internal Sub-module Control Error Handling and Watchdog Clocking Scheme Physical Implementation Verification and Validation 5
EIC-AncBrain Block Diagram GCLK clk_SCLM Clock Driver/ Buffer GLK_n_i generate_reset SC_in 2 Broadcast Signal Generator CML SC_in_i GRST_b_p_i GRST_b_n_i GRESET generate_sync rx_data_lpgbt [67:0] 2 Transceiver SYNC To next AncASIC clk_5M SYNC_p_i SYNC_n_i Clock Divider ( n) module_addr[2:0] Address Comparator Serial to Parallel Converter FSM address_match mux_sel_LAS Header Parser Manchester Encoder IDLE encoded_LAS_data rst_n AncASIC_ID[2:0] (hardwired) RECEIVE_HEADER default value (0) payload[39:0] payload[39:0] Parallel to Serial Converter data_type[1:0] ADDRESS_CHECK Data Mux LAS Serial Transmitter LAS_tx_data_i LAS_data_out data_type[1:0] 2 CL_in DECODE_DATA CML CL_in_i tx_data_las [39:0] Command Decoder tx_data_LAS [39:0] LAS_payload[39:0] 2 error_lpGBT error_LAS Transceiver PROCESS_LAS/ INTERNAL/ BROADCAST SC_SRV_WR_p_i To next AncASIC ctrl_internal SC_SRV_WR_n_i error_internal SC_CORE_WR_p_i Register File enable _signals SEND_RESPONSE clk_SCLM FSM_reset Clock Recovery / Synchronization SC_CORE_WR_n_i ERROR rst_n error_active LAS Response Timeout Counter Clock Domain Crossing / Synchronization timeout_flag timeout_flag Centralized Error Handler error_lpGBT error_LAS error_internal SC_SRV_RD_p_i FSM_reset_5M Parallel to Serial Converter error_flag_LAS SC_SRV_RD_n_i mux_sel_lpGBT tx_data_lpgbt[67:0] LAS_data_in SCL MHz 5 MHz SC_CORE_RD_n_i error_response[67:0] LAS_response_formatted Data Mux SC_CORE_RD_p_i Serial to Parallel Converter SC_out_i received_LAS_data LAS Data Buffer LAS Serial Receiver rx_data_las [39:0] LAS_rx_data_i rx_data_las [39:0] NBVG & SLDO read_data to SC_out 2 Temperature Sensor T_Critical (hardwired) Temp Temp Threshold Comparator NBVG Watchdog Timer Alternative Power Supply CML 2 Manchester Decoder Transceiver watchdog _flag 1.2V Supply Over- AncASIC From SLDO (x4) Temperature Flag System Clock (SCLM=160MHz or 320MHz??) Slow Control Clock (5MHz) Error Signals Sub Modules and Support Data Processing and Control Unit LAS Interface lpGBT Interface 8
AncASIC System-Level Design and Implementation Flow System Requirements lpGBT/LAS Protocol Design Constraints Icon Status Timeline AncASIC Design Power Management and Bias Voltage Control (NBVG & SLDOs) Communication with lpGBT (receive transaction, transmit response) Communication with LAS (Service/ Core Management, Broadcast) Robust Error Handling Radiation Tolerance (Triplication) Communication Protocol to LAS REQ01-1-1 to REQ01-4-1 Specifications Power Budget: ? (mW) Area limit: 8 mm2 ?? Timing: Global Clock = 160/320 MHz ? Max LAS Response Time: ? (ms) Done - Underway March 25 30 To be done May 25 Behavioral Modeling (SystemVerilog) Functional Verification Digital Synthesis Synthesize RTL using Genus Generate gate-level netlist Implement Design Constraints Optimize the design for area, power, and performance Functionality Check Digital Implementations Place & Route using Innovus Check for blockage, congestion Meet timing, power and area constraints Functionality Check Specification & Architecture Digital Design Simulation using Xcelium Simulator Coverage Analysis (IMC) Assertion Checks FSM, Command Decoder, Data Buffers lpGBT Interface Logic (Serializer and Deserializer) LAS Interface Logic (Manchester, Serial Tx/Rx) Error Handler (TimeOut, Parity/CRC, Manchester, Temperature) **RTL Coding (DVT Eclipse, Catapult) Define transaction formats (68-bit, 40- bit) Protocols (lpGBT, LAS) FSM Error Code Register Maps **AncASIC Documentation 30 30 **Target: 100% Code Coverage Sub-module Design (Schematics) NBVG SLDOs (Collaborators from RAL,LBNL) Temperature Sensor Clock Divider (System Clock to 5 MHz) CML Transceivers (x3) (SC_in, SC_out, CL_in) Watchdog Alternate Power Supply Layout & Physical Implementation Functional Verification Spice Simulation of Sub-modules Corner Case Analysis Noise and Signal Integrity Checks Analog Design Custom Layout of Sub-Modules DRC/LVS Checks Parasitic Extraction **Schematic design using Virtuoso **Adhere to design rules, optimize area and performance Post Triplication Verification Static Timing Analysis (STA) Power Analysis Signal Integrity Checks Back-annotation of Parasitics DRC/LVS Checks Triplication Combined Verification Final AncASIC Integration and Triplicate FSM and other critical logic blocks using TMRG Re-synthesize Placement using radiation aware- constraints Tapeout Documentation Static Timing Analysis (STA) Power Analysis Signal Integrity Checks Back-annotation of Parasitics DRC/LVS Checks Final Steps 9 30 30 30 30 **Meet timing closure, analyze power consumption **SEU mitigation **Release to fabrication
Design Verification hardware emulation Software Mockup (BNL) needed for functional verification before implementation to verify code coverage, find exceptional situations, and reduce risks single step implementation. Hardware mockup (LBL) needed to perform verification in experiment like environment Both included in FY25 eRD113 s deliverables 11
Digital Verification: Digital Twin and Hardware Verification In Summary: These mockups are intermediate milestone towards ensuring the success of our digital work (that has some analog components still) hence full implementation. 12
Thank You 13
