Enhancing Memory Access Latency with Advanced Controllers
This research focuses on accelerating cache misses through an improved memory controller, addressing latency in accessing main memory. The study delves into the intricacies of memory access latency, highlighting the components impacting performance. Through detailed analysis, the study showcases the benefits of a compute-capable memory controller in reducing effective memory access latency, offering insights for optimizing system performance.
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Presentation Transcript
Accelerating Dependent Cache Misses with an Enhanced Memory Controller Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt Tuesday June 21: Session 7A, 3:30pm
Memory Access Latency The latency of accessing main memory is made up of two parts: Multiprocessor DRAM
Memory Access Latency The latency of accessing main memory is made up of two parts: DRAM access latency Multiprocessor DRAM
Memory Access Latency The latency of accessing main memory is made up of two parts: DRAM access latency On-chip latency Multiprocessor DRAM
On-Chip Delay 100% 90% 80% Total Miss Cycles 70% 60% 50% 40% On-Chip Delay 30% 20% DRAM-Access 10% 0% 4xcalculix 4xpovray 4xastar 4xgamess 4xmilc 4xgcc 4xh264ref 4xbzip2 4xcactus 4xwrf 4xleslie 4xmcf 4xtonto 4xgromac 4xXalancbmk 4xzeusmp 4xomnetpp 4xsoplex 4xsphinx 4xbwaves 4xGemsFDTD 4xperlbench 4xlbm 4xlibquantum 4xnamd 4xhmmer 4xsjeng 4xgobmk 4xdealII
Dependent Cache Misses Cache Miss LD [R3] -> R5
Dependent Cache Misses Cache Miss LD [R3] -> R5 ADD R4, R5 -> R9
Dependent Cache Misses Cache Miss LD [R3] -> R5 ADD R4, R5 -> R9 ADD R9, R1 -> R6
Dependent Cache Misses Cache Miss LD [R3] -> R5 ADD R4, R5 -> R9 ADD R9, R1 -> R6 Cache Miss LD [R6] -> R8
Effective Memory Access Latency Reduction 450 400 Effective Memory Access Latency 350 300 250 Core Access 200 150 100 50 0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Mean
Effective Memory Access Latency Reduction 450 400 Effective Memory Access Latency 350 300 250 EMC Access 200 Core Access 150 100 50 0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Mean
Accelerating Dependent Cache Misses with an Enhanced Memory Controller Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt Tuesday June 21: Session 7A, 3:30pm
