Exploring BEL-level CAD on Xilinx FPGAs with RapidSmith
Dive into the world of BEL-level CAD exploration on Xilinx FPGAs using RapidSmith. Discover the frameworks, limitations, and improvements in modifying Xilinx XDL designs. Explore tools for converting netlists, modifying design packing, and more to enhance your FPGA projects.
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Presentation Transcript
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs Travis Haroldsen Brent Nelson Brad Hutchings D E P A R T M E N T O F FPGA 2015 Feb 22-24
RapidSmith 1 Framework for modifying Xilinx XDL designs Contain components and routing of Xilinx chips Supports large number of research topics including Rapid design prototyping flows Reliability and fault-tolerant techniques PR frameworks Post-PAR debug FPGA security 2
RapidSmith 1 Limitations RapidSmith uses string attributes to describe slice-level functionality Little information about the types of BELs in a site Hinders BEL-level manipulations BXINV::#OFF F:frame_buf/VGA/r_regVS<4>_rt:#LUT:D=A1 FFY_SR_ATTR:#OFF COUTUSED::0 _BEL_PROP::G::PK_PACKTHRU CYSELG::G YUSED:#OFF CYINIT:CIN GNDF:ProtoComp1.GNDF.1 FXMUX::FXOR 3
RapidSmith 2 Improvements Adds BEL types, properties, and interconnectivity New BEL-level netlist Tools to convert between XDL and BEL-level netlist Allows modifying the packing of a design Provides functionality for packing, placing, and routing a synthesized netlist onto Xilinx FPGAs 4
