FPGA Memory Synthesis Techniques

Synthesis of Memories in FPGA Patrick Schaumont

Overview Design flow for Datapath and Memory Elements Inference and instantiation Integrated synthesis and simulation Memory Elements Register Files SRAM in Cyclone V E FPGA

Design flow for datapath & memory elements Automatic Selection of Library Components (by matching a Verilog language pattern) RTL Verilog Manual Selection of Library Components (by matching a module type name) Inference Instantiation Macro's Elements which can be expanded in terms of primitives Libraries Primitives Elements directly available in the FPGA fabric LUT2 L(O, I1, I2); Netlist FPGA fabric Bitstream LUT2 MULT BRAM

Example 1 (primitive): Flip-flop This piece of code infers a flip-flop module fsmdesign(input wire i, clk, output reg q); always @(posedge clk) q <= i; endmodule

Example 1 (primitive): Flip-flop This piece of code instantiates a flip-flop module fsmdesign(input wire i, clk, output reg q); dff mydff(i, clk, 1'b1, 1'b1, q); endmodule This is a primitive library element

How do we know what primitives are available?

How do we know what primitives are available?

Inference vs Instantiation Standard design practice (for any type of digital design: FPGA, ASIC) will mix inference and instantiation Inference: Portable code which compiles on multiple targets Portable code which simulates with generic simulator Provides maximal freedom to synthesis tools Instantiation: Nonportable code which makes specific assumption on target Nonportable code which requires simulation library to simulate Gives designer maximum control over synthesis process

Integrated Synthesis and Simulation Once we use design elements from a library, we need to add a simulation library specific to the target technology Simulation library may provide a behavioral model of primitives and macro's, to implement the leaf cells of your design In addition, after synthesis, additional design details help to estimate precisely the delay incurred by each component and each net. This can also be included in the simulation. Simulation library may provide detailed structural model of primitives, which are decorated with delay figures from tools.

Overview Design flow for Datapath and Memory Elements Inference and instantiation Integrated synthesis and simulation Memory Elements Register Files SRAM in Cyclone V E FPGA

Memory Elements: Register Files Used when multiple registers are attached to single bus May be multi-ported and/or concurrent read/write R1 write address read address R2 write data read data R3 write address2 MUX read additional write ports additional read ports address2 R4 write data2 read data2 How to implement this ?

Memory Elements: Register Files Single write-port : load-enable edge-triggered reg write decoder address enable write data R1 module r1(q, clk, enable, in); output [7:0] q; reg [7:0] q; input clk, enable; input [7:0] in; always @(posedge clk) if (enable) q <= in; endmodule

Memory Elements: Register Files How to implement dual write-port ? write address2 write address1 enable write data2 write data1 R1

Memory Elements: Register Files Dual write-port : load-enable edge-triggered reg, mux and priority write decoder address2 write decoder address1 enable write data2 write data1 0 R1 1 What is the (most likely) critical path of this design ?

Memory Elements: Register Files Dual write-port : load-enable edge-triggered reg, mux and priority write decoder address2 write decoder address1 enable write data2 write data1 0 R1 1 What is the (most likely) critical path of this design ? Multi-port registers are slower than single-port registers

Overview Design flow for Datapath and Memory Elements Inference and instantiation Integrated synthesis and simulation Memory Elements Register Files SRAM in Cyclone V E FPGA

Memory Modules in Cyclone V

Inferring RAM in Verilog // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [5:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [63:0]; // 16-bit, 64 locations reg [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr]<=di; do <= RAM[addr]; end end endmodule

Inferring RAM in Verilog // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [5:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [63:0]; // 16-bit, 64 locations reg [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr]<=di; do <= RAM[addr]; end end check your expectations endmodule

Inferring RAM in Verilog // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [1:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [3:0]; // 16-bit, 4 locations reg [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr]<=di; do <= RAM[addr]; end end endmodule

Inferring RAM in Verilog // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [1:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [3:0]; // 16-bit, 4 locations reg [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr]<=di; do <= RAM[addr]; end end endmodule no block memory!

What if we use asynchronous RAM read ? // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [5:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [63:0]; // 16-bit, 64 locations wire [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di; end end assign do = RAM[addr]; endmodule

What if we use asynchronous RAM read ? // default: single-port synchronous RAM module my_ram (clk, en, we, addr, di, do); input clk; input we; input en; input [5:0] addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [63:0]; // 16-bit, 64 locations wire [15:0] do; always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di; end end assign do = RAM[addr]; endmodule no block memory!

Dual-port RAM module my_ram (clk, we, r_addr, w_addr, di, do); input clk; input we; input [5:0] w_addr, r_addr; input [15:0] di; output [15:0] do; reg [15:0] RAM [63:0]; // 16-bit, 64 locations reg [15:0] do; always @(posedge clk) begin if (we) RAM[w_addr] <= di; do <= RAM[r_addr]; end endmodule

Initialized RAM An initialized RAM can be used as a lookup table or as a ROM In FPGA, bitstream specifies the initial contents of the M10K In Verilog, we may specify the initial contents of the RAM in diffferent ways using initial block (inference) or synthesis constraints (instantiation) using $readmemb or $readmemh system calls The tools will then ensure that the RAM will be initialized to the specified state after configuration

Finding how to write HDL for memory

Overview Design flow for Datapath and Memory Elements Inference and instantiation Integrated synthesis and simulation Memory Elements Register Files SRAM in Cyclone V E FPGA