FPGA System Design Final Project - Sort Algorithm Implementation on FPGA Boards
Explore the detailed final project idea involving implementing and testing a sort algorithm on FPGA boards. Learn about utilizing Block RAMs, initializing data from external files, and displaying sorted results using UART. Dive into specific requirements such as handling unsigned 16-bit data inputs and supporting both increasing and decreasing order sorting. Additionally, discover another project idea focusing on utilizing the Integrated Logic Analyzer (ILA) for debugging FPGA designs and documenting the process. Team up with a partner for project management and schedule a project review for demonstration in the final exam week.
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Presentation Transcript
CDA 4253 FPGA System Design Final Project Hao Zheng Comp Sci & Eng U of South Florida 1
Final Project Idea 1 Implement and test a sort algorithm on FPGA boards. Unsorted data are stored in Block RAMs. Initialization of the Block RAMs should be done through an external file. After the sorting is finished, the sorted data are displayed in a terminal on the host system through a UART transmitter (study Chapter 7 about UART interface). 2
Final Project Idea 1 uart_start UART TX uart interface Ctrl uart_done sort_start addr sort_done din din N dout N Sort Memory k addr we 3
Final Project Idea 1: Specific Requirements Data inputs are unsigned and 16-bit wide. Data inputs are defined in hexadecimal format in an external file to initialize the block RAM. The minimal size of data inputs should be >= 16. The sorted results displayed on the terminal through UART are also in hexadecimal format. Your design should support the selection of sorting in an either increasing or decreasing order. 4
Final Project Idea 2 Study and use the Integrated Logic Analyzer (ILA) for debugging designs. ILA is a hardware component that can capture hardware traces while the a target system is executing. The captured HW traces can be viewed as waveform for debugging. Objective: Get familiar with ILA, know how to use it to debug an FPGA implement with defects. 5
Final Project Idea 2 At the end, Demonstrate by fixing a buggy design, Submit a report detailing the entire process of using ILA to fix the bugs. Documents: Vivado Design Suite Tutorial: Programming and Debugging (UG936) Vivado Design Suite User Guide: Programming and Debugging (UG908) Integrated Logic Analyzer v5.0 (PG172) 6
Final Project Management Each team has up to two members. Make sure you find a partner you can work with. Both team members get the same project grade. Project Review Each team schedules a project review in the final/final exam week. Demonstration the successful completion of the chosen project. Your design may be required to re- configured on-site to verify its correctness. A written report is due at the end of review. 7
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