Front-end Electronics for Silicon Vertex Detector
Explore the detailed specifications of the front-end electronics for a Silicon Vertex Detector, including sensor numbers, ladder numbers, read-out channels, ASIC parameters, and possible solutions for ASIC read-out. Learn about the current SPD Si module prototype and the serial read-out diagram, showcasing the cutting-edge technology in this field.
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Presentation Transcript
Silicon Vertex Detector Front-end electronics 25.03.2021
Relevant FEE DAQ numbers # layer 1 (MAPS) 2 (MAPS) 3 (MAPS) 4 (DSSD) 5 (DSSD) Total Sensor numbers /layer 448 840 1736 228 368 596(DSSD) + 3024(MAPS) Ladder numbers 11 20 28 19 23 101 Sensor numbers /stave (module) 28 28 28 2 2 Numbers stave (modules)/layer 16 30 62 114 184 Numbers e-links/stave 8 8 8 Numbers analog MUX- OUT/module 10 10 Read-out channels / layer 128 e-links 240 e-links 496 e-links 1140 1840 864 e-links + 2980 analog MUX-OUT 2
Current SPD Si module prototype BM@N Si-Module DSSD parameters: Polyimide microcables (300 and 600 mm length) - - Size: 63x63x0.3 mm3(on 4 FZ-Si wafers) Topology: double side microstrip (DSSD) (DC coupling) Pitch p+strips: 95 m; Pitch n+strips 103 m; Stereo angle between p+/n+ strips: 2.50 Number of strips: 640 (p+) 614(n+) - - - - DSSD The module consists of one silicon detector, glued to the frame and connected with front-end electronics via thin polyimide cable. FEE based on VATAGP7.1 ASICs 3
Parameters of read-out chips ASIC VATAGP7.1 Number of CSA Input charges (dynamic range) Peaking time (slow shaper) Peaking time (fast shaper) Noise (ENC) Lowest threshold (no capacitance) 128 channels 30 fC 500 ns (typ.) 50 ns 70e +12e/pF (typ.) 0.12 fC Voltage supply +1.5V, -2.0 V Gain from input to output buffer (diff. output currents) Output Serial analog multiplexer clock speed Power dissipation per channel 16.5 A/fC 3.9 MHz 2.2 mW 4
Serial read-out diagram Detector Silicon IDEAS ASICs VATAGP7.1 ADC Multichannel > 50 MSPS Control Unit Based on FPGA Front end electronics DAQ System 5
Possible solutions for ASIC read-out ASIC APV25 VATAGP7.3 n-XYTER TIGER ToASt Channels number 128 128 128 64 64 Dynamic Range -40fC 40fC -30fC 30fC Input current 10nA Polarity - and+ 59.4 mV/fC 1 50fC 1 40fC Gain 25mV/fC 20 A/fC 10.35mV/fc ToT gain 40ns/fC 246e-+36 e-/pF 70e-+12 e-/pF 900e-at 30pF 2000e-at 100pF 1500e- Noise Peaking time 50ns 50ns/500ns 30ns/ 280ns 60ns/ 170ns 50 / 100ns Power consumption 1.15mW/ch. 2.18mW/ch. 10mW/ch. 12mW/ch. 4mW/ch. ADC No No 16fC, 5 bit 10-bit Wilkinson ADC 8 bit TDC No No Timestamp resolution < 3.125ns Timestamp resolution < 5ns Timestamp resolution < 6.25ns 6
