Future Trends in GPU and Manycore Computing
Explore the latest advancements in GPU and manycore computing, featuring sessions on accelerators, cloud computing, invited speakers discussing applications, benchmark evaluations, and the future of computing with thousands of cores on a single chip.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.
E N D
Presentation Transcript
Session 1: GPU: Graphics Processing Units Miriam Leeser / Northeastern University HPEC Conference 15 September 2010 MIT Lincoln Laboratory HPEC-1
Manycore is Here to Stay Current accelerators of choice: Multicore processors (2, 4 or 8 processors on a chip) Graphics processing units (GPUs) NVIDIA, AMD Cloud computing The future: Manycore processors (16, 32, 64 processors on a chip) More flexible GPUs AMD Fusion, NVIDIA Fermi, Intel Knight s Corner Cloud computing on a chip Intel s Single Chip Cloud Computer MIT Lincoln Laboratory HPEC-2
This Mornings Talks Invited speakers: Accelerating Mechanical Computer Aided Engineering (MCAE) applications with GPUs Dr. Robert Lucas, USC ISI Thinking outside the Tera-Scale box Piotr Luszczek, University of Tennessee at Knoxville GPUs: Sparse Matrix Algorithms on GPUs and their Integration into SCIRun Devon Yablonski, Northeastern University Benchmark Evaluation of Radar Processing Algorithms on Graphics Processor Units (GPUs) Scott Sawyer, Lockheed Martin Failing In Place for Low-Serviceability Infrastructure Using High-Parity GPU-Based RAID Anthony Skjellum , University of Alabama at Birmingham MIT Lincoln Laboratory HPEC-3
The Future Manycore computing and GPUs: From dozens to thousands of cores on a single chip SIMD: Single Instruction Multiple Data Vector processing Network on a chip A mix of styles CPU, GPU, Programming techniques, languages, methodology ? MIT Lincoln Laboratory HPEC-4
