Gem5 Integration in SST Simulation Toolkit at Sandia National Labs
Explore the integration of Gem5 in the Structural Simulation Toolkit (SST) at Sandia National Labs, aiming to become the standard architectural simulation framework for HPC. The project focuses on providing gem5 functionality within the SST Framework, with goals to evaluate future systems and enhance supercomputer design using parallel core components. Current release focuses on improving documentation, introducing more component models, and ensuring interoperability with key tools like DRAMSim and cache models.
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Presentation Transcript
Structural Simulation Toolkit / Gem5 Integration + + ARM Research, Sandia National Labs Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy s National Nuclear Security Administration under contract DE-AC04-94AL85000.
View of the Simulation Problem Scale..... Many Cores + Memory Many Many Many Threads Many Many Nodes X X Multiple Audiences..... Network Processor System X system procurement algorithm co-design architecture research language research Application writers purchasers designers X X present systems future systems Complexity..... Communication Libraries Run-Times OS Effects X X Multi-Physics Apps Informatics Apps Existing Languages New Languages Constraints..... Performance Cost Power Reliability Cooling Usability Risk Size
SST Simulation Project Overview Goals Become the standard architectural simulation framework for HPC Be able to evaluate future systems on DOE/DOD workloads Use supercomputers to design supercomputers Status Parallel core, standard components Current Release (4.0) Improved documentation More component models Technical Approach Parallel Parallel Discrete Event core with conservative optimization over MPI Multiscale Detailed and simple models for processor, network, and memory Interoperability gem5, DRAMSim, cache models routers, NICs, schedulers, GPGPU Open Open Core, non viral, modular Consortium Best of Breed simulation suite Combine Lab, academic, & industry
SST Components Processors Ariel PIN-based Prospero Trace-based Miranda Pattern-based Memory MemHierarchy Caches, memory VaultSimC - Stacked memory Cassini Cache prefetchers Network drivers Ember Pattern-based Firefly communication protocols Hermes - MPI-like driver interface Zodiac trace-based Network models Merlin Network simulator Scheduler Missing: Detailed Execution-based Core Model
Integration Goals Provide gem5 functionality in the SST Framework Interoperability w/ other components Parallelism Previous integration (2011) was with a branch of Gem5 Emulation mode only Not sustainable New integration is with the main Gem5 stable release Ability to run full-system Testing of the new integration is underway
Integration Issues gem5 Clock / Events Untimed (functional) accesses Can t cheat - everything must be timed Memory events Forwarding snoop requests to core Compilation issues (the usual)
Studies PIM Normalized Execution Time 1.375 Better Processing-in-memory Multi-Level Memory HW Tradeoffs: capacity ratios, prefetching/transfer SW Tradeoffs: application, runtime, OS, HW control Scalable Network Studies Network on Chip Coherent system interconnect NIC Mixed Mode Simulation 1.1 1.07 1 1 1 1 1 0.99 0.825 0.84 0.84 0.69 0.67 0.55 0.54 0.54 0.50 0.50 0.275 0 GUPS Stream PF MiniFE Lulesh
Summary Gem5 will be able to use SST s infrastructure and components Provides SST components with excellent core model Provides gem5 with a parallel discrete event framework Sustainable Current code committed Testing underway
