
Hardware Design and IC Lab Overview at National Taiwan University
Explore hardware design and IC lab topics at National Taiwan University's Graduate Institute of Electronics Engineering. Learn about basic and advanced hardware concepts, such as Verilog, RTL coding, synthesis, and common design issues.
Download Presentation

Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.
E N D
Presentation Transcript
Media IC and System Lab Graduate Institute of Electronics Engineering National Taiwan University Hardware basic & advance Speaker: Shao-Syuan Huang( ) Media IC & System Lab 1
Reference Reference Slide from Hung-Chang Lu Slide from NCTU ICLAB course Media IC & System Lab 2
Outline Outline Design flow overview Verilog basic introduction Hardware advance topic Media IC & System Lab 3
Outline Outline Design flow overview Verilog basic introduction Hardware advance topic Media IC & System Lab 4
HDL vs Software Language HDL vs Software Language Media IC & System Lab 5
Cell-Based IC Design Specifications RTL Coding RTL code Front-End Synthesis Gate-level netlist DFT Insertion ATPG Place and Route Test Patterns DRC LVS GDS Layout Back-End Layout Tape Out Media IC & System Lab 6
Circuit Abstraction Media IC & System Lab 7
RTL simulation RTL simulation Testbed.v Design.v Media IC & System Lab 8
Common issues Common issues ncverilog testbed.v design.v +access+r to dump waveform +notimingcheck if using SRAM $fsdbDumpvars(0,"+mda") to dump all memory signal, including 2D array Media IC & System Lab 9
Synthesis Synthesis Map your RTL code to standard cell Optimization to meet timing constraint Static timing analysis (STA) Media IC & System Lab 10
RTL vs Gate-Level RTL sel 1 in2 out 0 in1 Gate-level a2_o in2 a2 out in1 o1 a1_o iv_sel a1 sel n1 Media IC & System Lab 11
Gate Gate- -level simulation level simulation Use the same pattern in RTL simulation Dynamic timing analysis (DTA) Media IC & System Lab 12
Outline Outline Design flow overview Verilog basic introduction Hardware advance topic Media IC & System Lab 13
Combinational & Sequential Sequential Part Combinational Part in1 sel 1 out 0 clk in2 clk Memory-less Always running clk Media IC & System Lab 14
Sequential Part Describe the behavior of sequential circuit always @ ( <sensitivity edge > <clock> [or <sensitivity edge> < reset >] ) if ( reset ) ; // reset mode else ; // normal mode Asynchronous reset Synchronous reset rst D Q next_count count clk Media IC & System Lab 15
Asynchronous & synchronous reset Asyn reset reset at the posedge of reset signal Syn reset reset at the posedge of clock signal Syn reset no reset occurs Media IC & System Lab 16
Metastability The unstable status due to non ideal data transition is called metastability. Media IC & System Lab 17
Setup time & Hold time Setup time(Tsu) : the minimum amount of time the data signal should be held steady before the clock. Hold time (Th) : the minimum amount of time the data signal should be held steady after the clock Media IC & System Lab 18
Critical Path Critical path is the path that has longest delay between reg or in/out in the whole circuit. Delay: 5ns Delay: 3ns clk clk clk Media IC & System Lab 19
Pipeline Pipeline Delay: 4ns Delay: 4ns clk clk Delay: 4ns Delay: 4ns clk clk clk Media IC & System Lab 20
Input buffer Input buffer Input Delay 4ns Delay: 4ns clk Input Delay 4ns Delay: 4ns clk clk Media IC & System Lab 21
Clear control Clear control Circuit Controlling Unit Processing Unit Media IC & System Lab 22
Finite State Machine (FSM) IDLE down =1 ZERO DOWN count=0 Media IC & System Lab 23
Finite State Machine (FSM) Media IC & System Lab 24
Common issues Data type reg is NOT definitely to be a register. Instead, the synthesis result depends on the described behavior of RTL. Multiple Driven Signals issue The variable of data type wire can NOT be repeatedly assigned. The variable of data type reg can only be assigned in single always block. x x Media IC & System Lab 25
Common issues Avoid appearance of Latch during synthesis. Latch is too advanced for beginner of digital circuit. Latch is due to incomplete assignment in combinational part. Incomplete assignment implies that circuit will hold the previous Usage of positive & negative clock simultaneously is NOT recommended. Timing issue will cause the poor performance if not design properly. Complicated clock tree for skew issue during place and route. Media IC & System Lab 26
Outline Outline Design flow overview Verilog basic introduction Hardware advance topic Design ware Memory System verilog Media IC & System Lab 27
Design ware Design ware IP(Intellectual Property) Hard IP: GDSII format Firm IP: Netlist resource Soft IP: RTL design In Media 11 Datasheet and manual are in /opt/CAD/synopsys/synthesis/2019.12/dw/doc/ Media IC & System Lab 28
Design ware Design ware RTL behavior simulation Absolute path: `include /opt/CAD/synopsys/synthesis/2019.12/dw/sim_ver/DW_sqrt.v" Relative path: `include "DW_sqrt.v ncverilog tb.v design.v -incdir /opt/CAD/synopsys/synthesis/2019.12/dw/sim_ver/ Synthesis Usage Media IC & System Lab 29
Memory Memory Media IC & System Lab 30
SRAM SRAM Slower but has less area than register Only one address can be accessed in same time(single port SRAM) Media IC & System Lab 31
DRAM DRAM Off chip memory, Read/Write latency penalty is huge Data burst Media IC & System Lab 32
SystemVerilog SystemVerilog - - Logic data type Reason: The datatype isn t equal to the real circuit. reg doesn t mean a register. It depends on how you use these variables. So, in SystemVerilog, a new type logic is introduced to replace both of them. reg for procedural assignment (within always block) Flip-Flop must be the data type of reg wire for continuous assignment (assign) module MyModule( input wire a, output reg b, input wire c, output wire d, module MyModule( input logic a, output logic b, input logic c, output logic d, Media IC & System Lab 33
SystemVerilog SystemVerilog - - always blocks Replace all always@(*) by always_comb Replace sequential always block by always_ff Media IC & System Lab 34
SystemVerilog SystemVerilog - - build build- -in function in function $clog2() ceil(log2(x)) Someday you write: parameter MAX_NUM = 6; parameter BIT_NEED = 3; // 6 requires 3 bits logic [BIT_NEED-1:0] counter; Another day: parameter MAX_NUM = 100; // You amend parameter BIT_NEED = 3; // Then, you forgot it The systemverilog version: parameter BIT_NEED = $clog2(MAX_NUM); Media IC & System Lab 35
SystemVerilog SystemVerilog - - Enum & unique case Media IC & System Lab 36
SystemVerilog SystemVerilog - - type define Media IC & System Lab 37