Hardware/Software Techniques for Minimizing Data Movement Workshop
This workshop focuses on innovative ideas and techniques to reduce data movement in hardware and software systems. Topics include Near Data Processing, In-Memory Computing, Cache/DRAM Optimizations, Data Compression, and more. Keynotes, peer-reviewed papers, and insightful discussions by industry experts make this workshop a valuable resource for researchers and professionals in the field.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.
E N D
Presentation Transcript
Min-Move 2017 1stWorkshop on Hardware/Software Techniques for Minimizing Data Movement
Organizers Adwait Jog Assistant Professor, College of William and Mary Computer Architecture, GPUs, Memory Systems www.cs.wm.edu/~adwait EJ Kim Associate Professor, Texas A&M University Computer Architecture, Interconnects, Performance Evaluation http://faculty.cse.tamu.edu/ejkim/ 2
Scope Any idea/technique that can help in reducing the data movement is appropriate for this workshop. Some topics (but not limited to) are: Near Data Processing (e.g., near caches or memory or storage devices) In-Memory Computing (e.g., in caches or memory or storage devices) Approximate Computing (e.g., load value approximations) Cache/DRAM Locality Optimizations Data Compression Techniques Emerging Memory Technologies (e.g., STT-RAM, Memristor) Non Von-Neumann Architectures (e.g., Quantum Architectures, Automata Processor) Interconnection Architectures (e.g., on-chip, off-chip, Ethernet, interposer system, flexible interconnects for FPGA) Programming and Language Support for Minimizing Data Movement 3
Program Committee Murali Annavaram (USC) Rajeev Balasubramonian (Utah) Reetuparna Das (UMich) Lizy Kurian John (UT Austin) David Kaeli (Northeastern) Onur Kayiran (AMD) Hyesoon Kim (Gatech) Asit Mishra (Intel) Lawrence Rauchwerger (Texas A&M) Sudhakar Yalamanchalli (Gatech) 4
Highlights of the Workshop Keynotes from Lizy Kurian John (UT Austin) Yan Solihin (NSF/NCSU) Jun Yang (UPitt) Peer-Reviewed Workshop Papers (most of the papers received three reviews) Exploring Non-Uniform Processing In-Memory Architectures (UT Austin) Evaluating a Trade-Off between DRAM and Persistent Memory for Persistent-Data Placement on Hybrid Main Memory (Fujitsu Laboratories) Opportunities for Processing Near Non-Volatile Memory in Heterogeneous Memory Systems (UIUC and AMD) 5
Workshop Schedule 6 http://insight-archlab.github.io/minmove.html
