High-Level Synthesis for Data Acquisition in Zynq UltraScale+ based AMC
Explore the use of high-level synthesis languages like C and OpenCL for simplifying data acquisition and processing in Zynq UltraScale+ based Advanced Mezzanine Cards (AMCs). Learn how these languages can enhance hardware development, reduce development time, and improve scalability in FPGA applications.
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Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages A. Pi as, C. Gonz lez, M. Ruiz, A. Carpe o Universidad Polit cnica de Madrid a.pinas@upm.es Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 1 EPICS Collaboration Meeting. April 2025
Outline 1. Introduction Data acquisition in MicroTCA Motivation OpenCL and HLS 2. Proposed system Hardware Platform Software Platform 3. Use case Digital Pulse Shape Analysis 4. EPICS Integration 5. Summary 6. About us Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 2 EPICS Collaboration Meeting. April 2025
MicroTCA Hardware Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 3 EPICS Collaboration Meeting. April 2025
Typical AMC-based data acquisition application Custom or manufacturer dependent drivers for communication Custom HDL Low level Long development time Limited flexibility/scalability Maintainability Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 4 EPICS Collaboration Meeting. April 2025
Goal and motivation Simplify the development process for DAQ applications in FPGAs Let HDL aside for application development, using C-like high-level synthesis languages (HLS) to describe hardware Higher abstraction Reduce development time Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 5 EPICS Collaboration Meeting. April 2025
Xilinx-AMD acceleration methodology Main elements: Host program, written in C/C++, runs on a CPU (external or embedded) and makes calls to the OpenCL API to communicate with the hardware Kernels describe hardware functions, written in C/C++ (HLS) or OpenCL, that are implemented in the FPGA Host and kernels exchange data through global memory Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 6 EPICS Collaboration Meeting. April 2025
Xilinx-AMD acceleration methodology - Platforms This method requires a basic infrastructure, called Platform. Users can develop custom platforms for Zynq-based boards! Hardware Platform (Static FPGA region) (Mandatory) AXI for kernel control and global memory access (Mandatory) Clocks, resets, interrupts (Optional) AXI Stream Interfaces + (Optional) Application-specific hardware (e.g. ADC/DAC interface, PCIe ) ARM Software Platform. A single Linux kernel module (zocl) takes care of everything! (Kernel execution management, buffer allocation, memory transfer ) Libraries for accelerated applications + Application-specific sources (drivers, libraries, etc ) Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 7 EPICS Collaboration Meeting. April 2025
Implemented Hardware Platform Driver available (https://github.com/Xilinx/dma_ip_drivers) JESD204B Analog Devices open-source IP blocks 4 TX/RX lanes @ 8 Gbps (easily scalable) The JESD204B signals are routed to the FMC connector, to which a loopback card is connected PCIe connectivity 4 Lanes Gen3 @ 8 GT/s XDMA AXI Stream mode 2 DDR4 memory banks Kernels can use the Processing System memory or an independent memory bank 2 Ethernet interfaces AXI Interconnectivity for kernel control and data movement Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 8 EPICS Collaboration Meeting. April 2025
Software Platform Embedded Linux developed using Petalinux (Yocto-based) Xilinx Runtime Library included in the meta-xilinx layer Analog devices layers (meta-adi) Linux device drivers that manage JESD204 peripherals as well as ADC/DAC and clock chips Drivers are synchronized through a Finite State Machine for proper link bring-up Board support layer provided by NAT Required device-tree nodes (JESD204B drivers and zocl) added in the user layer, meta-user Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 9 EPICS Collaboration Meeting. April 2025
Example use case Digital Pulse Shape Analysis Implementation and verification of a DPSA (Digital Pulse Signal Analysis) algorithm to extract physically relevant parameters from the signals provided by BC501A liquid scintillator Starting point: Algorithm written in C++ for offline analysis (Spanish Fusion Lab, CIEMAT) Validation using signals coming from a real dataset (sampling rate 1GS/s) Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 10 EPICS Collaboration Meeting. April 2025
Use case Digital Pulse Shape Analysis Signal Generation *for verification using real datasets Sampling rate 1GS/s 1. FIR filter and constant factor of discrimination NAMC-ZYNQ-FMC ZYNQ-Ultrascale+ MPSoC PS PL OUTSTREAM 128 TX AXIS_TX JESD204B HOST Loopback CH0 128 INSTREAM 128 DPSA RX AXIS_RX 2. Peak detection = Time, # of peaks per signal and pileups 3. Energies calculation = Integrate over several time intervals GLOBAL MEMORY Data acquisition Full article for details: https://www.researchgate.net/publication/380114731_Hardware_Acceleration_of_Digital_Pulse_Shape_Analysis_Using_FPGAs Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 11 EPICS Collaboration Meeting. April 2025
EPICS Integration NDSv3 + NDS-EPICS Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 12 EPICS Collaboration Meeting. April 2025
Summary Implementation of a XILINX VITIS platform in an AMC for data acquisition (JESD204B) and processing using HLS/OpenCL Abstraction from the hardware, focus on the algorithm The platform can be easily migrated to other Zynq UltraScale+ MPSoC based AMCs Implementation of a use case (pulse analysis) demonstrating DAQ/Processing Nice setup to emulate real experiments conditions Use of standard Linux Kernel drivers (zocl and xdma) and APIs to manage the hardware Simplified EPICS integration with NDS Use of open-source components for JESD204B (IP blocks, Linux Kernel drivers) Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 13 EPICS Collaboration Meeting. April 2025
About us The Instrumentation & Applied Acoustics research group (I2A2) is part of the Polytechnic University of Madrid (UPM). Currently celebrating 25 years of research and innovation. The I2A2 research group is specialized in: Embedded Systems Real-Time Systems Hardware Acceleration EPICS Device Drivers and Support Tight relationship with ITER, IPP, CIEMAT Learn by Doing We're Open to Collaborations Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 14 EPICS Collaboration Meeting. April 2025
Github Request access if you are interested https://github.com/i2a2/namc_zynqup_fmc_bsp/tree/ad_jesd204_2021.1 Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 15 EPICS Collaboration Meeting. April 2025
Questions? Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 16 EPICS Collaboration Meeting. April 2025
Acknowledgements Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 17 EPICS Collaboration Meeting. April 2025
Workflow and development tools Platform Hardware platform Vivado Software platform Petalinux Application Kernel compilation Vitis HLS Host compilation Cross compiler Linking and Packaging Vitis Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 18 EPICS Collaboration Meeting. April 2025
Resource utilization BSP (DAQ interface, PCIe ) DPSA Implementation Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 19 EPICS Collaboration Meeting. April 2025
JESD204B Implementation Physical and Data Link layers implemented using Analog Devices HDL Library. Open- source solution for implementing JESD204B links Transport and application layers implemented using HLS HDL HLS Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 20 EPICS Collaboration Meeting. April 2025
JESD204B subsystem Each peripheral has an AXI-Lite based configuration interface Samples are sent/received through AXI Stream interfaces JESD204B signals are routed to the FMC connector Data acquisition and processing for Zynq UltraScale+ based AMCs using high-level synthesis languages. 21 EPICS Collaboration Meeting. April 2025
