HPS DAQ Updates and Future Development at Jefferson Lab

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Explore the latest updates on HPS DAQ system achievements and requirements at Thomas Jefferson National Accelerator Facility. Learn about the status of the Calorimeter and Hodoscope readouts, as well as the ongoing development efforts for future runs including new TIpci boards. Stay informed about the cutting-edge technology and advancements in data acquisition.

  • HPS DAQ
  • Jefferson Lab
  • Data Acquisition
  • Accelerator Facility
  • Technology

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  1. HPS DAQ updates Sergey Boyarinov JLAB Nov 18, 2020 Thomas Jefferson National Accelerator Facility Page 1

  2. HPS DAQ & Trigger Requirements 20kHz event rate 100MB/s data rate >95% livetime Achieved event rate 27kHz Thomas Jefferson National Accelerator Facility Page 2

  3. HPS DAQ/Trigger Front-End Electronics Calorimeter (Upper Half) Calorimeter (Bottom Half) FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC FADC ROC ROC VTP VTP SD SD TI TI HPS1 ROC HPS2 ROC faraday Hodoscope (bottom half) Hodoscope (upper half) to Event Builder to Event Builder L1 TRIG L1 TRIG to Event Builder TI TIpcie ROC TD SD clonfarm2 ROC TS HPS11 ROC CLK 250MHz, TRIG, SYNC to TIs BUSY to TD to Event Builder to Event Builder TIpcie clonfarm3 ATCA crate ROC 3 VXS crates, 2 servers, 1 ATCA crate, 7 Readout Controllers Thomas Jefferson National Accelerator Facility Page 3

  4. HPS DAQ Status - Calorimeter Readout: 442 channels of 12bit 250MHz Flash ADCs - Hodoscope Readout: 32 channels of 12bit 250MHz Flash ADCs - CPU/VTP/TS/SD/TD trigger and signal distribution boards - 3 VXS crates - 2 servers with TIpcie cards for SVT readout - SVT readout (front-end and ATCA blades) Back-end computing and software is CLAS12 facility: network, computing, DAQ software, data monitoring, messaging system, realtime database Thomas Jefferson National Accelerator Facility Page 4

  5. Main development for future run Two new TIpci boards were received from production and currently under testing TIpci was tested in servers where old version failed, and it works now, servers recognize it as standard PCI device Library being developed More boards will be produced, then we will be able to send one to SLAC SVT readout have to be adjusted using new TIpci boards Thomas Jefferson National Accelerator Facility Page 5

  6. New TIpcie module Better PCIe compatibility: Xilinx UltraScale+ FPGA: xcku3p PCIexpress from gen1x1 (low power) to gen3x8 (high bandwidth) More like a VME TI: TI fiber#1, fiber#5 40-pin IO to the second front panel 8 outputs + 1 clock output; (LVDS, 3 optional ECL) 10 inputs + 1 clock input; (any diff. level) More potentials: Another 64 LVDS connection to the FPGA: 64-channel FPGA based TDC USBC connector on the front panel +5V in for standalone operation Two prototypes under testing, more boards are ordered Thomas Jefferson National Accelerator Facility Page 6

  7. DAQ Status All hardware and software on JLAB side is ready to run any time, except new TIpci boards SVT part is removed Integration with SVT DAQ has to be repeated again because of new TIpcie module, it has to be discussed and planned (test setup at SLAC) If SVT readout performance improved we can increase overall DAQ performance (without SVT, DAQ can run >30kHz) Thomas Jefferson National Accelerator Facility Page 7

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