I/O Systems and Operations in Operating Systems CS550

I/O Systems Operating Systems CS550

I/O Systems OS controls I/O devices and operations Important to realize this when designing an OS There are standardized SW/HW interfaces But, there are also increasing varieties of IO devices

I/O Hardware I/O Hardware Many types of devices Disk/tape for storage Network/bluetooth for storage Human interface devices (screen, keyboard, mouse, audio) Some are more specialized (steering wheel for car, gas pedal, jet controls, etc.)

How does I/O happen? How does I/O happen? Communication between device and computer occurs over a port If communication is over a shared set of wires, this set of wires is called a bus May occur via Daisy Chaining Ex: Device A is connected to device B and device B connects to device C, where C is a computer. This chain may be a bus

Different Buses Different Buses PCI bus (common system bus) connects CPU, graphics card, disk controllers, and other fast devices A SCSI (Small Computer Systems Interface) bus is sometimes used for disks as is SATA (Serial Advanced Technology Attachment) drives. Both SCSI and SATA have complex controllers that are attached to the PCI bus These allow for bad sector mapping, prefetching, buffering and caching These controllers have their own processors and circuit boards CPU allows for I/O transfer by sending bytes/words over I/O ports directly to the registers of the I/O controller by selecting the proper lines on the bus This can also occur by memory mapped IO - e.g. writing screen data from the graphics controller directly to a specific memory area

I/O Ports I/O Ports 4 registers 4 registers 1. data in - read by host device to get input 2. data out - written to by host to get output 3. status - bits indicating command completion, data availability in data-in register, device errors, etc. 4. control - written to by host to start a command or change device mode (e.g. switching from full duplex to half, switching speeds, error checking, etc.) o Often 1-4 bytes in size and controller may hold small amounts of data temporarily

Polling Polling Handshaking occurs between host and controller Could use 2 bits to have producer consumer relationship Command-ready Busy set means change to 1 clear means change to 0 Controller sets busy bit while working and clears when ready for commands Host (e.g. CPU) signals need to execute command by setting command ready

Algorithm: Algorithm: 1. Host busy-waits (polls) for busy bit to become clear 2. Host sets write bit in control register and writes a byte to data out 3. Host sets command ready bit 4. Controller checks command-ready and sets busy bit 5. Controller reads command register and sees write command in control register It reads data out and does I/O to the device 6. Controller clears command ready and clears error bit (success) and clears busy bit

Interrupts Interrupts CPU has an interrupt request (IRQ) line that is checked after every instruction On signal from a controller, CPU saves state and performs an interrupt handler routine Dev. controller raises interrupts by signaling IRQ CPU catches the interrupt and dispatches it to the interrupt handler 100's or 1000's managed per second Need to handle during critical processing Need to dispatch without polling Need priority levels Have interrupt controller HW Nonmaskable interrupts - e.g. memory errors - can't be hidden Maskable interrupts - can be turned off/ignored

Interrupts (Contd..) Interrupts (Contd..) Interrupts are often chained Have interrupt vector pointing to head of list of handlers Call handlers one by one until one is able to service the request Ex. Page faults cause interrupt to block a process until memory I/O can be performed Interrupts also occur in SW and are called SW interrupts or traps These may identify particular system services or kernel operations to run Cause a process to save state and block Have lower priority than device interrupts

Direct Memory Access (DMA) Direct Memory Access (DMA) Also has handshaking via DMA requests and acknowledge operations Stops CPU from accessing main memory when transferring file to or from memory This is called cycle stealing Notice that this requires an interrupt process

I/O Review I/O Review Basic components needed are bus controller I/O port and registers Handshaking between device and controller Execution of handshaking in polling loop or with interrupts Offloading work to a DMA controller for large transfers