Improved Random Pattern Delay Fault Coverage Using Inversion Test Points
This article discusses the concept of improved random pattern delay fault coverage by leveraging inversion test points. It explores the challenges of pseudo-random testing, random pattern resistant faults, motivation to detect such faults, and methods to enhance pseudo-random pattern tests. The conventional test-point architecture is examined, along with its detriments in detecting stuck-at faults. Overall, the focus is on enhancing fault coverage in testing methodologies for better reliability.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.
E N D
Presentation Transcript
Improved Random Pattern Delay Fault Coverage Improved Random Pattern Delay Fault Coverage Using Inversion Test Points Using Inversion Test Points Soham Roy, Brandon Stiene, Spencer Millican and Vishwani Agrawal
Pseudo-random Test Practical B Built-I In-S Self-T Test scheme Cheap Simple In-field Widely used in previous and current technologies. Quality degraded due to undetected hard- to-detect faults, sometimes called as R Random P Pattern R Resistant faults. Low fault coverage. Pseudo-random pattern gen. (PRPG) i.e. LFSR Inputs, memory Test enable Multiplexer Circuit under test (CUT) Outputs, memory Response compactor i.e. MISR 2
Random Pattern Resistant Fault Random pattern resistant faults 32 1 1 1 1 . . . . . . . . 1 1 1 1 32 0 0 0 0 . . . . . . 0 0 0 0 Stuck-at-1 1 232;????.?? 32 0 ? 1 232;????.?? 32 1 ? 264;????. ?? 32 1 ? ??? 32 0 ? {Highly improbable P (Exciting Stuck-at-1 on OR gate) = P (Propagating Stuck-at-1 on AND gate) = 1 P (Detection of Stuck-at-1) = Highly improbable} 3
Motivation: To detect random pattern resistant faults Motivation: To detect random pattern resistant faults Methods to improve pseudo-random pattern test: Deterministic seeding Pattern weighting T Test-p point i insertion Test-point: A hardware modification to enhance testability which may change in logic functionality when active. Methods to improve test-point insertion Location selection algorithms Enable selection algorithms Test-point implementation/architecture 4
Conventional test-point architecture 32 32 Stuck-at-0 TPE 32 32 TPE Stuck-at-1 Control-0 test-point Control-1 test-point 32 32 Stuck-at-1 TPE: Test-point enable Observe test-point Observe J. Rajski and J. Tyszer, Arithmetic Built-in Self-test for Embedded Systems. Upper Saddle River, NJ, USA: Prentice-Hall, Inc., 1998. 5
Detriments of Conventional test-point architecture Stuck-at fault model Faults masked Faults masked An active control TP forces a line to a set value, only one stuck-at value can be excited when a control test- point is active preventing logic on the controlled signal from passing through the test-point. Control TPs prevent signal transitions and will block all delay faults from passing through the TP. Control test points prevent delay faults on the output of the TP from being excited. 32 Stuck-at-0 TPE 32 TPE: Test-point enable 6
Detriments of Conventional test-point architecture Transition delay fault model 32 An active control TP forces a line to a set value, only one stuck-at value can be excited when a control test- point is active preventing logic on the controlled signal from passing through the test-point. Control TPs prevent signal transitions and will block all delay faults from passing through the TP. Control test points prevent delay faults on the output of the TP from being excited. TPE Control-1 32 Output normal Output faulty Output TP TPE: Test-point enable Observe 7
Inversion-based test-point architecture Stuck-at fault model 32 32 Control Control- -Invert 90% Invert TPE When TP When TP= = OFF Signal Probability = = 10 Stuck- -at at- -0 0 ( (Signal Probability Signal Probability = = 90 OFF Stuck Stuck- -at at- -1 1 ( (Signal Probability Stuck 10%) %) 90%) %) When TP When TP= = ON Signal Probability = = 90 Stuck- -at at- -0 0 ( (Signal Probability Signal Probability = = 10 ON Stuck Stuck- -at at- -1 1 ( (Signal Probability Stuck 90%) %) 10%) %) TPE: Test-point enable Y. Fang and A. Albicki, Efficient testability enhancement for combinational circuit, in Proceedings of International Conference on Computer Design (ICCD), Oct 1995, pp. 168 172. 8
Inversion-based test-point architecture Transition delay fault model 32 TPE 32 TPE: Test-point enable 9
Detriments of inversion-based test-point architecture Possible detriments of inversion- based test point architecture 32 32 50% 50% TPE 50% TPE 32 100% 32 Faults masked Faults masked Faults propagate Faults propagate TPE: Test-point enable 10
Test-point insertion algorithm For every test-point, calculate controllability (CC) and observability (CO) for every line. Generate candidate test- points Start Fault coverage calculation. No Satisfy target fault coverage or the number of test- points Yes Pick best test-point. [List- based search] End Insert test-point into circuit. H. C. Tsai, K.-T. Cheng, C. J. Lin, and S. Bhawmik, A hybrid algorithm for test point selection for scan-based BIST, in Proceedings of the 34th Design Automation Conference, June 1997, pp. 478 483. 11
Stuck-at fault coverage for 65,536 vectors 100 95 Fault coverage (%) 90 85 80 75 b04 b05 b07 b11 Benchmark circuits b12 b13 c432 c1355 c2670 c3540 No TPs Conv. Inv. ITC 99 and ISCAS 85 benchmarks 12
Transition delay fault coverage for 65,536 vectors 100 95 90 85 Fault coverage (%) 80 75 70 65 60 55 50 b04 b05 b07 b11 Benchmark circuits b12 b13 c432 c1355 c2670 c3540 No TPs Conv. Inv. ITC 99 and ISCAS 85 benchmarks 13
Test-point insertion CPU seconds 400 350 300 250 200 Time (s) 150 100 50 0 b04 b05 b07 b11 b12 b13 c432 c1355 c2670 c3540 CPU: Intel core i7-8700 RAM: 8 GB Clock: 3.2 GHz Benchmark circuits Conv. Inv. ITC 99 and ISCAS 85 benchmarks 14
Conclusion Inversion test-points compared to conventional control test-points. Conclusions and Future Directions No negative impact on stuck-at fault coverage. Increase delay fault coverage. 15
Future Directions Impact of observe test points on delay fault detection. Conclusions and Future Directions Impact of test-points on the detection of redundant faults and producing false failures. 16
Thank You 17
