Improving DRAM Latency with Charge-Level-Aware Techniques

reducing dram latency via charge level aware look n.w
1 / 6
Embed
Share

Learn about a novel approach to reducing DRAM latency using charge-level-aware look-ahead partial restoration. This method addresses the significant portion of DRAM access latency caused by cell restoration processes, leading to notable performance gains and energy savings.

  • DRAM Latency
  • Charge-Level-Aware
  • Performance Improvement
  • Energy Reduction
  • Technology
rayaanacharya
jveron Follow

Uploaded on | 0 Views

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

You are allowed to download the files provided on this website for personal or commercial use, subject to the condition that they are used lawfully. All files are the property of their respective owners.

Download Presentation

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author.

E N D

Presentation Transcript

  1. Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration

  2. Problem DRAM Cell Restoration latency takes up to 43.6% of DRAM access latency Activation Restoration Refresh Row buffer Page 2 of 6

  3. Motivation Observation: a recently-accessed row is likely to be accessed again soon Page 3 of 6

  4. Our Proposal Page 4 of 6

  5. Results 14.7% performance improvement 11.3% energy reduction Page 5 of 6

  6. Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration Session 3-A, Oct 22

Related


The Organization of DRAM Subsystem Components

The Organization of DRAM Subsystem Components

mallory
Memory Organization in Computers

Memory Organization in Computers

capri
Computer Architecture: Understanding SRAM and DRAM Memory Technologies

Computer Architecture: Understanding SRAM and DRAM Memory Technologies

klay
SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Processing Using DRAM

SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Processing Using DRAM

khadija
Experimental Lightning Flash Prediction and Verification Study

Experimental Lightning Flash Prediction and Verification Study

petal
Real-time Experimental Lightning Flash Prediction Report

Real-time Experimental Lightning Flash Prediction Report

omaira
Analyzing and Improving Latency in IEEE 802.11 Networks

Analyzing and Improving Latency in IEEE 802.11 Networks

constanc
Memory Management and Swapping Techniques

Memory Management and Swapping Techniques

alijah
Insights into DRAM Power Consumption and Design Concerns

Insights into DRAM Power Consumption and Design Concerns

emberly
Enhancing Memory Cache Efficiency with DRAM Compression Techniques

Enhancing Memory Cache Efficiency with DRAM Compression Techniques

trav_45
Architecting DRAM Caches for Low Latency and High Bandwidth

Architecting DRAM Caches for Low Latency and High Bandwidth

fpiro
Managing DRAM Latency Divergence in Irregular GPGPU Applications

Managing DRAM Latency Divergence in Irregular GPGPU Applications

mayt_93
Panopticon: Complete In-DRAM Rowhammer Mitigation

Panopticon: Complete In-DRAM Rowhammer Mitigation

monta
Understanding DRAM Errors: Implications for System Design

Understanding DRAM Errors: Implications for System Design

arta766
Lightning Validation Tools and User Feedback in Lightning Data Analysis

Lightning Validation Tools and User Feedback in Lightning Data Analysis

martyngo
Challenges and Solutions in Memory Hierarchies for System Performance Growth

Challenges and Solutions in Memory Hierarchies for System Performance Growth

yoandrice
Understanding Latency Variation in Modern DRAM Chips

Understanding Latency Variation in Modern DRAM Chips

glei
Latency Measurement in IEEE 802.11 for Low Latency Applications

Latency Measurement in IEEE 802.11 for Low Latency Applications

argo_nka
Real-time Experimental Lightning Flash Prediction for Lightning/TS Forecast

Real-time Experimental Lightning Flash Prediction for Lightning/TS Forecast

airon
Virtual Memory and its Implementation

Virtual Memory and its Implementation

tian836
Enhancing DRAM Performance with ChargeCache: A Novel Approach

Enhancing DRAM Performance with ChargeCache: A Novel Approach

migisi
Intelligent DRAM Cache Strategies for Bandwidth Optimization

Intelligent DRAM Cache Strategies for Bandwidth Optimization

igart

More Related Content