Interconnection Structures: Common Bus Systems Explained
Discover the functioning of common bus multiprocessors in computer systems, their limitations, and the concept of time-shared common bus structures. Explore the implementation of dual bus systems for efficient data transfer. Learn about local buses, system bus controllers, and memory sharing among processors in a shared bus environment.
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Presentation Transcript
Interconnection Structures Presented by A.Srinivasan, Assoc Professor
Time Shared Common Bus A common bus multiprocessor consist of number of processors connected through common path to a memory unit. In this only one processor can communicate with memory or another processor at a given time. Any other processor wishing to initiate a transfer, must first determine the availability status of the bus and then can initiate the transfer. A command is issued to inform the destination unit that operation is to be performed. The receiving unit recognizes its address in the bus and responds to the control signal from sender, after which the transfer is initiated.
Time Shared Common Bus A single common bus system is restricted to one transfer at a time. Ex: One processor is communicating with the memory, all the other processor are either busy with internal operation or must be idle waiting for bus. Total overall transfer rate with in the system is limited by the speed of the single bus. The processors in the system can be kept busy by implementing two or more independent buses that permits simultaneous bus transfer. The dual bus structure is shown below
Time Shared Common Bus In this it consist of local buses, each connected to its own local memory and to one or more processors. Each local bus may be connected to CPU, IOP or any combination of processors. A system bus controller links each local bus to a common system bus The memory connected to common system bus is shared by all processors.
