Introduction to VHDL Coding Basics
Explore the fundamental concepts of VHDL coding with examples in Xilinx ISE Design Suite, covering entity declaration, port definition, architecture body, project setup, and implementation like full adders. Learn how to create new projects, set project configurations, and generate VHDL code templates using software tools.
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Presentation Transcript
Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee
Outline Example of Example of VHDL Coding in Xilinx ISE Design Suite VHDL Coding in Xilinx ISE Design Suite Basic Knowledge of VHDL Basic Knowledge of VHDL
Outline Example of Example of VHDL Coding in Xilinx ISE Design Suite VHDL Coding in Xilinx ISE Design Suite Basic Knowledge of VHDL Basic Knowledge of VHDL
Example of VHDL Coding in Example of VHDL Coding in Xilinx Xilinx ISE Design Suite ISE Design Suite Work Flow Work Flow The figure shows the software tools in a logic design project from schematic to VHDL code to *.bit file for download to BASYS or BASYS2 board.
Project Settings Choose TQ144 if you are using a BASYS board
Generated VHDL file template by the software: Generated VHDL file template by the software: Entity declaration (Entity name) Port definition (Port name and direction) Architecture body (Write the functions here!)
Outline Example of Example of VHDL Coding in Xilinx ISE Design Suite VHDL Coding in Xilinx ISE Design Suite Basic Knowledge of VHDL Basic Knowledge of VHDL
Basic Modeling Constructs Entity declarations Entity declarations Entity identifier: Lab00 Ports definition Ports definition Port names: A, B, Cin, S, Cout Port directions in for input ports, out for output ports. Architecture body Architecture body Architecture identifier: Behavioral Behavioral descriptions Behavioral descriptions Signal assignment statement S <= <= A xor B xor Cin; ; Logical operators and, or, not, and, or, not, xor xor, , nand (No difference between upper case and lower case.) Use ( ) ( ) to make the statement clearly expressed. nand, nor, , nor, xnor xnor
Signal Assignment Statement Example Example = + X ABCD ABCD Logical operators in lower case Logical operators in upper case Less parentheses ( )
Assign Logic 1 and Logic 0 Example Example Y = X = 0 1 Assign value of 1 Assign value of 0
