Investigation of Methods to Reduce Services Load for EIC MAPS Detector
The overall plan of eRD104 involves investigating methods to significantly reduce the services load for an EIC MAPS-based tracking detector by focusing on powering and data aggregation aspects. Current status includes an initial study on power reduction architectures, with plans to build upon this assessment in FY22. Research aims to optimize viable systems for minimizing service loads due to signal transmission.
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eRD104 Silicon Services Reduction eRD111 Si-Vertex (excl. sensors) R&D proposals from the EIC Silicon Consortium (and LANL for eRD111) ERD104 https://drive.google.com/file/d/1qkXA-oA3nigDVWiC83pEq1RbFw4EzdCu/view?usp=sharing ERD111 https://drive.google.com/file/d/1EWf-F-GvzuijadqsPZMNtIgB8_K423aH/view?usp=sharing eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 1
eRD104 Overall Plan Services Reduction intent is to investigate methods to significantly reduce the services load for an EIC MAPS based tracking detector. This can be broken down into the largest components: Powering Investigate the use of DC-DC converter based architectures to significantly reduce the number of wires needed to power the detector. This will require that we introduce radiation tolerant DC-DC converters into the detector structure in proximity to the disc/stave connection points. Investigate the use of serial powering architectures with the same effect. This will require that we introduce regulation at the (stitched) sensor level either on die or as a hybrid arrangement. Assess detector design goals and apply the best overall optimization of available technologies studied under R&D to the final implementation of the detector (tracking and others who are interested in working on this) Data Investigate the use of data aggregation on detector using radiation tolerant FPGAs to receive multiple data streams from sensor blocks (over twinax) and multiplex and transmit the data out via high speed fiber ribbon connections to RDO boards. This will require functionality in the MUX boards to steer control and configuration and additional power for the MUX boards in detector. Again, the final R&D goal is to develop a optimized viable system for minimizing the services loads due to signal transmission. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 2
Current Status An initial study examining both serial powering and DC-DC converter based architectures with a goal of quantifying the service reductions that could be realized with these architectures was completed and is available as a technical note. https://www.eicug.org/web/sites/default/files/Powering-options-for-an-EIC-silicon-tracker.pdf Depending on the architecture chosen, service reductions for powering cables can possibly be reduced by up to ~90%. In order to form plausible services estimates to integrate into the simulation effort a simple DC-DC based architecture was explored and documented in: https://docs.google.com/presentation/d/17s4u7ZiU2djTYH0MMF5DJvVKqFU5fzPY/edit?usp=sharing&o uid=105418108496832762190&rtpof=true&sd=true The work on multiplexing is currently in the conceptual stage. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 3
FY22 Plans points of discussion This is documented in our proposal, here are the main points for discussion: Build upon the initial assessment of possible benefits of serial/DC-DC converters powering schemes and detail possible configurations with analysis of architectural benefits/weaknesses and assessment of current and upcoming DC-DC converter candidates in written report form. Single branch construction, testing and characterization of existing DC-DC converter candidates in likely architectures with written report. This work can be extended to other detector configurations/needs with appropriate consultation and architectures/requirements. Research into existing serial powering schemes used by ATLAS and other experiments with analysis and extrapolation into EIC case. If feasible, get example hardware and characterize. Otherwise examine on-chip or hybridized regulators. Examination of capabilities of components needed for multiplexing (rad-hard FPGAs and optical modules) and preliminary studies of the tradeoffs in architectural approaches. Written progress report. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 4
Schedule, Budget and Milestones Milestone Description Date report on serial powering 2022/04/29 report on DC-DC powering 2022/06/24 FY22 assessment report on powering options 2022/09/29 erd104 FY22 report 2022/09/30 Topic Institutions involved Contact Person Powering System University of Birmingham, STFC RAL PPD Laura Gonella (Univ of Birmingham), Fergus Wilson (RAL) Additional collaborators are most welcome in these tasks. Please let us know if you have interest. Budget broken out by institutions will be generated this week. Readout system ORNL, BNL Jo Schambach (ORNL) eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 5
Introduction The goal of the EICSC is the development of a full tracking detector solution composed of next generation 65 nm process MAPS sensors and based on the developments ongoing at CERN for the ALICE ITS-3. We have identified areas of R&D that require development that are particularly challenging and/or extend beyond the existing MAPS implementations and need a program of extended R&D in order to be ready for application to a EIC MAPS tracking detector. These areas are the focus of our proposal. Forming modules from stitched sensors Stave/disc construction Additional infrastructure including mechanics and cooling eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 6
Overall Plan Forming modules from stitched sensors The formation of block units of sensors with which to fabricate staves and discs is essential to allow for efficient fabrication of these structures. Experience shows that this is a very large task involving complex precision tooling and assembly machines (custom pick and place, bonders, aluminum conductor FPC, electrical design, etc.) as well as a well designed and developed process and supply chain management system. In ALICE ITS-2 (10 m^2 of silicon) we required 6 assembly sites working for 2 years to complete the fabrication. The R&D for this process took an additional 3 years. We need to begin exploring this task in the EIC context as soon as is reasonable and possible. Our goal is to form a technical and organizational plan for this. Stave/disc construction The development of staves and , in particular, discs that are optimized for the EIC environment can/may lead into new directions and mechanical and electrical solutions. Some are described in our R&D plan, others may be developed as the R&D plan moves forward. The goal of this RD plan is to explore the mechanical/electrical stave and disc design space and then to select and optimize a design that best meets the EIC needs, to prototype and demonstrate feasibility, and to ultimately produce the staves and discs for the EIC. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 7
Overall Plan Additional infrastructure including mechanics and cooling It is required that the tracking detector mechanical structure and assembly/insertion mechanisms be aligned with the overall detector project need and constraints. This will take continuous effort, a shared CAD model and working together on mutually acceptable solutions. The cooling aspects are another area where some initial efforts via LDRD have been started at LBNL and ideas on air cooling using carbon foam between face sheets may prove to be quite helpful for both stave and disc designs. The cooling systems for silicon tracking in EIC are expected to consist of air and water cooling. If we are successful in the implementation of DC-DC converters or serial powering there will be additional dissipation that will need removed. The goal for the cooling is a complete and optimized thermal solution for the final tracking detector design. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 8
Current Status Forming modules from stitched sensors Initial conceptual ideas have been discussed. There are as yet no formal notes. Stave/disc construction Initial conceptual designs for staves and discs have been generated. Staves are based on ITS-2 truss structures. Discs can be based on CFC plate half discs or staves. Attributes with initial radiation length estimates have been generated and are presented at: https://docs.google.com/presentation/d/1GQ1WUq1N9uCmrb6mBwQQD9LY6XlLVbop/edit?usp=shari ng&ouid=117565418253641032508&rtpof=true&sd=true Additional infrastructure including mechanics and cooling A CAD mechanical model of the all-silicon tracking detector that fits with the current project structures and ideas on assembly has been generated and is being maintained as part of developing a common base for the proto-collaborations to use in generating their proposals. The path forward may be seen at: https://docs.google.com/presentation/d/1l0W1OyAZ1wP-LlK-mQUj7_Xh-ACv- d3C/edit?usp=sharing&ouid=117565418253641032508&rtpof=true&sd=true. The initial release notes of the CAD model may be found at: https://drive.google.com/file/d/1YkrkczEkO_izFamAVE5HLfBOE9uK8ZMq/view?usp=sharing. It is expected that this model will track with the changes in the detector design and project requirements. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 9
FY22 Plans points of discussion Sensors => modules 1. Study of how to adapt the ITS3 based mechanical and electrical characteristics to the nominal EIC vertexing layer radii based on the available reticle sizes, and optimization of the bending and interconnection techniques for the resulting configuration 2. Study of how to configure sensors into staves and discs based on reticle sizes and possible yield configurations on a 12 wafer. 3. Study of optimizing the number of stitched sensor units into a module composed of an aluminum flex PCB and optimized number of sensors. Flex PCB (aluminium conductor) manufacturing capabilities will play a significant role. Prototype designs may be run as a test fabrication and assessed. 4. The need for tooling to assemble and test sensors in module form will be investigated (this was a very significant part of the ALICE development for ITS2). 5. This will inevitably be a survey effort and will need to be further optimized once yield figures are known. Nevertheless this work is needed to form requirements for the large-area sensor design in a multiple sensor => single readout chaining. This will inform the functionality needed to be built into the forked sensor design. 6. A written report covering this will be delivered. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 10
FY22 Plans points of discussion Staves and discs 1. Conceptual designs with analysis ready to be prototyped. 2. Initial simple prototype proof of concept test pieces to be used in cooling and mechanical testing. 3. Written reports detailing the results and evaluating suitability for final design (parameters will inevitably change, but we need to evaluate the design concepts in the framework of the current knowledge). Mechanics, Integration and Cooling 1. Updated and maintained CAD model of evolving silicon tracking detector design in conjunction with EIC project detector constraints including beam pipe, assembly, integration envelopes, etc. 2. Design concepts for the full set of detector supports including cylinders, shells, services channels, connection points to global supports with detector assembly, integration, and connection to services aspects addressed. This will be in written form and in CAD model form. 3. Initial analysis of the design and possibly prototype pieces of the carbon fiber structures involved in the tracking detector as a written report. 4. Analysis of the cooling options for the staves and discs (vertexing layers are an ongoing topic with the ITS3 work). Preliminary design of water cooling options with segmentation and architecture. Investigation into and analysis of using air cooling in a sandwiched carbon foam configuration for staves and discs. All in written report form. If feasible, initial analysis prototypes and results with report in written form. eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 11
Schedule, Budget and Milestones Milestone Description Date report on modules options/optimizations 2022/08/08 report on baseline stave designs 2022/04/27 report on baseline disc designs 2022/06/08 report on simple disc and stave models 2022/12/21 (FY23) up-to-date silicon tracking CAD models 2022/06/15 report on mechanics conceptual design 2022/07/27 ERD111 report for FY22 2022/09/21 Topic Institutions involved Contact Person INFN Trieste, UK groups (Daresbury, Lancaster, Liverpool, Birmingham), INFN Bari Giacomo Contin (INFN Trieste) Domenico Elia (INFN Bari) Roy Lemmon (Daresbury) Forming modules from stitched sensors Additional collaborators are most welcome in these tasks. Please let us know if you have interest. Budget broken out by institutions will be generated this week. LBNL, LANL, INFN Trieste, INFN Bari, UK groups (Daresbury, Lancaster, Liverpool) Nikki Apadula (LBNL) Walter Sondhem (LANL) Roy Lemmon (Daresbury) Staves and Discs LBL, LANL, UK groups, JLAB, Ernst Sichtermann(LBNL) James Fast (JLAB) Mechanics, integration and cooling eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 12
Modules Staves and Discs Mechanics, integration and cooling eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 13
backup eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 14
Starting Point - ALICE ITS-2 Current state of the art for MAPS Powering architecture is LDO regulator generated power for staves delivered to modules (14 sensors) individually with Cu wires. Readout (data, configuration, control) is carried over samtec twinax cables with the same modularity. This service load has been parameterized for the expected ITS-3 based sensor power needs and is in the current simulations in the tracking workgroup for the all-silicon design. https://indico.jlab.org/event/400/contributions/6541/attachments/5397/6728/2 020_09_03_Si_workshop_LG_infrastructure.pptx eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 15
Motivation The vast majority of the services for the ITS-2 (see photograph) consist of the powering and readout cables. https://indico.jlab.org/event/400/contributions/6541/attachments/5397/6728/2020_09_03_Si_workshop _LG_infrastructure.pptx eRD104 and eRD110 R&D EICSC meeting - 2021_11_08 - LG 16
