Large-scale Wafer Failure Pattern Recognition
Discover the importance of IC in modern electronics, the challenges in semiconductor manufacturing, and the benefits of a system for wafer failure pattern recognition and similarity ranking. Explore diverse wafer patterns, such as Center, Donut, Edge-loc, and more, and learn how an automatic system can enhance efficiency and consistency in inspection. Save time and boost yield with a system that processes daily production capacity, identifies platform/recipe problems, and enables engineers to find and correlate similar failure causes quickly.
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Presentation Transcript
Wafer Failure Pattern Recognition and Similarity Ranking on Large-scale Datasets ( ) ( ) ( ) ( ) 1/15
Introduction (1/2) Importance of IC in modern life Electronics products have grown to become a 2 trillion USD industryworldwide* Big data on semiconductor manufacturing TSMC produced 14 million wafers in 2012 Primary concern for semiconductor manufacturing Yield improvement Wafer maps can be obtained via the CP (circuit probe) test Wafer map 25 20 15 *Chris A. Mack, Fifty Years to Moore sLaw ,IEEE Transactions on Semiconductor Manufacturing, Vol. 24, No. 2. , pp. 202-207, May 2011. 10 2/15 5 5 10 15 20 25
Introduction (2/2) Wafer maps have diverse patterns Center Donut Edge-loc Edge-ring 40 50 50 40 40 30 40 30 30 30 20 20 20 20 10 10 10 10 20 Random 40 60 20 Loc 40 20 40 60 10 20 30 40 50 Near-full Scratch 60 25 30 50 20 40 40 20 15 30 10 20 20 10 10 5 1020304050 5 10 15 20 25 20 40 60 10 20 30 Wafer maps are mostly inspected by human in TSMC Inefficient Inconsistent An automatic system is in demand 3/15
Benefits of Our System Wafer failure pattern recognition Our system takes about 1 hour to process daily production capacity (~40,000 wafers) of TSMC, saving 100 man-hours per day (25,000 man- hours per year). Engineers can identify platform/recipe problems rapidly according to the predicted patterns. Similarity ranking Our system takes about 5 seconds to search 1 million wafers Engineers can find wafers with similar patterns, and then identify correlation among lots of similar failure causes. Our system saves man-hours and boosts the yield directly! 4/15
Related Work Existing approaches Clustering based o E.g. Art1, self-organizing map F. L. Chen and S. F. Liu, A neural-network approach to recognize defect spatial pattern in semiconductor fabrication, IEEE Trans. Semiconduct. Manuf., vol. 13, no. 3, pp. 366 373, Aug. 2000. C.W. Liu and C.F. Chien, An intelligent system for wafer bin map defect diagnosis: An empirical study for semiconductor manufacturing, Engineering Application of Artificial Intelligence, vol. 26, pp. 1479-1486, 2013. Model-based clustering o Model linear, curvilinear, amorphous, or ring-shaped patterns with p.d.f. T. Yuan, W. Kuo and S. J. Bae, Detection of spatial defect patterns generated in semiconductor fabrication process, IEEE Trans. Semiconduct. Manuf., vol. 24, no. 3, pp. 392 403, Aug. 2011. Comparison to existing approaches Clustering based Model-based clustering Spatial analysis based signature The method proposed Enhanced feature based Rotation and scale invariant For large-scale datasets 5/15 Integration ranking with similarity
System Flowchart Feature extraction Similarity ranking Radon-based features Geometry-based features Feature database Search top -100 similar wafers Feature vector Wafer failure pattern recognition Find the most salient object in a wafer map SVM (stage 1) Model 1 Top-100 wafer maps with salient objects No Pattern exists? Top-100 wafer maps Yes Template matching Template matching SVM (stage 2) Model 2 6/15 Retrieved wafers Predicted pattern None
Feature Set 1 Radon-based Features Center Donut Edge-loc Center Donut Edge-loc 40 50 50 40 40 20 40 60 80 20 40 60 80 20 40 60 30 30 20 20 20 10 10 50 100 150 50 100 150 50 100 150 20 40 20 40 60 20 40 60 Edge-ring Loc Random Edge-ring Loc Random 60 25 40 20 20 40 60 80 10 20 30 20 40 60 40 15 20 10 20 5 50 100 150 50 100 150 50 100 150 1020304050 Scratch 1020304050 Near-full 5 10152025 None Scratch Near-full None 30 30 50 40 20 40 60 80 20 20 20 20 30 20 10 10 40 40 10 50 100 150 50 100 150 50 100 150 20 40 60 10 20 30 10 20 30 7/15
Feature Set 2 Geometry-based Features Step 1: Object finding Find the most salient object Original The most salient object Original wafer Highlighted Region 40 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 10 20 30 40 10 20 30 40 Step2: Geometric attributes estimation 51 attributes in total, such as max area, max perimeter etc. Line detection Find the ratio of failure dies along the outermost ring Polynomial curve fitting 50 70 45 50 40 45 60 35 40 50 30 35 30 40 25 25 20 30 20 15 20 15 10 10 10 5 5 8/15 10 20 30 40 10 20 30 40 50 60 70 10 20 30 40 50
Experimental Results - Failure Pattern Recognition (1/2) Dataset Edge- Loc 4233 Edge- Ring 11650 Total Center Donut Loc Near-full Random Scratch None Training set Test set 82633 5768 518 2641 113 1247 1082 55381 123806 635 189 1954 1275 2126 104 336 817 116370 Computation time Time per wafer The system can handle about 660000 wafers per day by a single PC Feature extraction 0.13 second Training time 0.0031 second Test stage 0.0009 second CPU Intel i7 2600 (4 cores) Memory 16 GB Recognition rates of the test set Recognition rate Stage 1: Pattern wafer detection 96.55% Stage 2: Failure patter classification 81.40% 9/15
Experimental Results - Failure Pattern Recognition (2/2) Stage 1 Stage 2 Predict Edge-Ring Edge-Loc Near-full Random Scratch Center Predict Donut Pattern Loc none 86.6% (547) 2.4% (15) 3.0% (19) 6.0% (38) 1.3% (8) 0.8% (5) Center 0 0 8.6% (16) 67.7% (126) 3.2% (6) 0.5% (1) 12.9% (24) 5.9% (11) 1.1% (2) Donut 0 98.2% (7302) 1.8% (134) Pattern 0.1% (2) 90.6% (1756) 4.9% (94) 1.9% (36) 1.1% (22) 1.4% (28) Edge-Loc 0 0 0.2% (3) 9.5% (117) 89.6% (1100) 0.1% (1) 0.1% (1) 0.5% (6) Edge-Ring 0 0 Label Label 10.0% (210) 1.3% (27) 15.8% (331) 0.0% (1) 67.7% (1419) 0.5% (10) 4.6% (97) Loc 0 3.6% (4142) 96.4% (112228) none 98.1% (102) 1.9% (2) Near-full 0 0 0 0 0 0 2.8% (9) 7.4% (24) 4.3% (14) 4.9% (16) 79.7% (259) 0.9% (3) Random 0 0 1.5% (12) 0.4% (3) 6.2% (49) 0.6% (5) 11.2% (89) 0.1% (1) 80.0% (635) Scratch 0 10/15
Experimental Results Similarity Ranking Search 518 wafers (0.75 s) Search 518 wafers (0.75 s) Search 1331075 wafers (5.27 s) Search 1331075 wafers (5.27 s) Query wafer Query wafer Retrieval is very efficient The result is stable for large-scale datasets 11/15
System Maintenance - Web Interface Error analysis Misclassified instance visualization Support vector instance visualization Support vector instances misclassified instances Donut Loc Center Loc Random Loc Scratch Loc Ground-truth relabeling Auto retraining 12/15
System Maintenance Automatic Documentation Generation We have built a Wafer Analysis Toolbox Toolbox documentation can be automatically generated from comments in the code Plot for each function s example can be updated with code automatically. 13/15
Conclusions Comprehensive experiments have been conducted over large-scale datasets Advantages of the proposed system Achieves high accuracy while preserving efficiency Can handle the future production capacity of TSMC Provides web interface for easy maintenance Currently used in TSMC Saves man-hours and boost the yield directly for TSMC 15/15
Thank you! 16/15
Demonstration Failure pattern recognition Demo Similarity ranking Demo System Maintenance Web interface Demo Automatic documentation generation Demo 1 Demo 2 17/15
