Life Cycle of Teaching and Research in EDA and IC Implementation Methodology by Andrew B. Kahng

A Life Cycle of Teaching and Research on EDA and IC Implementation Methodology Andrew B. Kahng Depts. of CSE and ECE UC San Diego abk@ucsd.edu http://vlsicad.ucsd.edu/~abk A. B. Kahng, 200813 CadenceLive academic track

Teaching and Research Teaching Research 2 A. B. Kahng, 200813 CadenceLive academic track

The Life Cycle Industry EDA Semiconductor Faculty Research Teaching Students My Lab My Courses 3 A. B. Kahng, 200813 CadenceLive academic track

The Life Cycle Industry EDA Semiconductor Faculty Research Teaching Students My Lab My Courses 4 A. B. Kahng, 200813 CadenceLive academic track

The Life Cycle Industry EDA Semiconductor Faculty Research Teaching Students My Lab My Courses 5 A. B. Kahng, 200813 CadenceLive academic track

Flows Industry Faculty EDA Tools, Problems Research $$ Semiconductor Training Teaching Full-Time Advising Teaching ABKGroup Ph.Ds ~40% CDNS ~20% QCOM Intern Lab Course Students 6 A. B. Kahng, 200813 CadenceLive academic track

Teaching: UCSD ECE 260B (CSE 241A) VLSI Integrated Circuits and Systems Design 130+ M.S./Ph.D. students enrolled in Winter 2020 Back-end IC implementation, PPA, tools/methodology issues 7 A. B. Kahng, 200813 CadenceLive academic track

ECE260B Labs LAB2 LAB1 .lib Circuit Simulation Synthesis LAB6 Power/IR Drop Estimation DC / Genus gate-level netlist RedHawk / Voltus VCD Floorplan Gate-level Simulation Placement .lef .spef LABs 3,4 .sdf CTS .def .spef Timing Analysis Routing RC Extraction Innovus Quantus Tempus LAB5 .lib Library Characterization 8 A. B. Kahng, 200813 CadenceLive academic track

Teaching: UCSD ECE 260B (CSE 241A) VLSI Integrated Circuits and Systems Design 130+ M.S./Ph.D. students enrolled in Winter 2020 Back-end IC implementation, PPA, tools/methodology issues Readiness for job / internship (IC, system companies) Required Cadence trainings: Innovus Block-level (badge), Basic STA Optional (extra credit): Tempus Signoff/Closure (badge), Genus Job and Research relevance: timely updates to content Machine learning, 3DIC, Power planning, Chip-package interface 9 A. B. Kahng, 200813 CadenceLive academic track

Guest Lectures Course Evolution 10 A. B. Kahng, 200813 CadenceLive academic track

Teaching: UCSD ECE 260B (CSE 241A) VLSI Integrated Circuits and Systems Design 130+ M.S./Ph.D. students enrolled in Winter 2020 Back-end IC implementation, PPA, tools/methodology issues Readiness for job / internship (IC, system companies) Required Cadence trainings: Innovus Block-level (badge), Basic STA Optional (extra credit): Tempus Signoff/Closure (badge), Genus Job and Research relevance: timely updates to content Machine learning, 3DIC, Power planning, Chip-package interface Challenging usage of tools, enablement Mini-implementation projects: leakage optimization, useful-skew CTS, 11 A. B. Kahng, 200813 CadenceLive academic track

Flows Industry Faculty EDA Tools, Problems Research $$ Semiconductor Training Teaching Full-Time Advising Teaching ABKGroup Ph.Ds ~40% CDNS ~20% QCOM Intern Lab Course Students 12 A. B. Kahng, 200813 CadenceLive academic track

Research in ABKGroup Main vectors IC physical design (entire career) Design for manufacturability (DFM) (1996-present) Semiconductor/Design technology, Product roadmapping (1996-2018) ML in EDA and IC Design (off and on, ~2000-present) Research style Linkages tosemiconductor design, technology organizations Especially since 2004: support/collaborators = EDA customers, not EDA companies Research style: in the trenches (sub-5nm + 3D pathfinding, P&R) Advocacy / service to EDA, semiconductor industries 13 A. B. Kahng, 200813 CadenceLive academic track

IR Drop Mitigation by Power Stapling Back-end-of-line (BEOL) resistance has increased dramatically in sub-10nm VLSI Vicious cycle caused by high resistance Power staples are short pieces of wires and vias that connect two or more adjacent (i.e., consecutive) VDD or VSS rails to mitigate IR drop 14 A. B. Kahng, 200813 CadenceLive academic track

IR Drop Mitigation by Power Stapling Post-placement insertion afterfixedplacement and routing? No penalties, but poor IR drop improvement Our approach (DATE-2019): dynamic programming (DP) based detailed placement optimization to improve power staple insertion Insert power staples after the placement perturbation Three strategies for power stapling (i) single-row optimization; (ii) double-row optimization with overlap (Meta-1); (iii) two-pass double-row optimization without overlap (Meta-2) Before After power staple insertion (Meta-2) Worst IR=65mV Worst IR=79mV 15 A. B. Kahng, 200813 CadenceLive academic track

PPA Improvement with R- and C-Optimized Libraries High resistance-aware optimization is a key to PPA optimization Sub-5nm: resistance-optimized cells have better performance (speed) with large loads Resistance-Optimized standard-cell Library (ROL) Mesh output pin e.g., add horizontal M2 shapes on original cells output pin Compared to traditional Cap-optimized cells, less delay when load is high Kth (ROL) = 17 Kth (COL) = 21 M2 M1 Routability penalty: quantified using PROBE2.0 Example cell layouts in FreePDK45: https://si2.org/open-cell-library/ 16 A. B. Kahng, 200813 CadenceLive academic track

ROCOCo: ROL/COL Co-Optimization for PPA Performance (speed) comparison with buffered wires 3 cases of buffered wires: COL-only, ROL-only, and COL+ROL Exhaustive enumeration of buffering solutions 10 candidate locations / 3 maximum buffer locations 5 Buffer types: X1, X2, X3, X4, X8 (10 types for COL+ROL) Window of opportunity for ROCOCo heavy optimization RED = COL-only BLUE = ROL-only GREEN = COL + ROL X1_ROL X8_ROL COL > ROL 20um 180um X1_COL X8_COL 20um 180um X1_COL X8_ROL COL < ROL 20um 180um 17 A. B. Kahng, 200813 CadenceLive academic track

Pathfinding of Design Enablement What is the design impact of scaling boosters? Library, BEOL stack, PDN strategy, device/wire and patterning choices, UCSD PROBE methodology Basic Idea: systematically and randomly tangle a starting placement until router DRVs > threshold. Amount of tangling that can be tolerated gives a K_threshold (Kth) measure of inherent routability of a given enablement v1.0 focus = BEOL stack; v2.0 adds FEOL, enablement, design NAND4_X1 (6T) least routable INV_X1 (8T) most routable Fine-grain quantification! 18 A. B. Kahng, 200813 CadenceLive academic track

Example: Pathfinding of Design Enablement Kth on y-axis: larger is better Quantified impacts of backside, sparse, etc. PDN strategies Tool A s router is stronger than Tool B s router 19 A. B. Kahng, 200813 CadenceLive academic track

PROBE2.0 Framework Technology and Design Parameters Overall Flow for PROBE2.0 Tech/Design Options Extension to FEOL Cell-level Routability Assessment Design-level Routability Assessment PROBE2.0 Framework includes: Technology and Design parameters Cell-level routability assessment Design-level routability assessment 20 A. B. Kahng, 200813 CadenceLive academic track

PROBE2.0: ML-based Kth Prediction PROBE2.0 costs runtime, disk space, #licenses ML-based Kth prediction: less compute, faster turnaround E.g., AutoML (H2O) gives high-quality ML-based regression models Average error in Kth prediction is ~0.35 21 A. B. Kahng, 200813 CadenceLive academic track

Auto-Tuning of SP&R for ML ASICs DARPA Real-Time Machine Learning program Goal: Hardware generators and compilers to enable fully automated creation of ML Application-Specific Integrated Circuits (ASICs) from high- level source code Design space exploration and pathfinding for ML architectures Challenge: Dial in entire implementation recipe for SP&R to obtain a Pareto-optimal final layout Focus: from connectivity to auto-generated floorplan .def Example: TABLA ML architecture (UCSD, Esmaielzadeh) Layout after placement Layout after routing fmax ~2GHz, DRC-clean Connectivity 22 A. B. Kahng, 200813 CadenceLive academic track

Conclusion Synergy between teaching and research Life cycle: faculty + course + lab + industry engagement Tools + training modules strengthen course Tools inseparable from research (in ABKGroup) How can we do better? Run more contests ! Relatively cheap to organize, host (my students organized ICCAD19 global routing contest) Long-lasting impacts on faculty courses, research efforts Share more real-life problems Gives students a sense of real-life challenges, makes courses / projects more meaningful Great filter to identify students who have passion and talent to work on real-life problems Work together to create a more virtuous life cycle for our field 23 A. B. Kahng, 200813 CadenceLive academic track

Happy to answer questions or have followup discussions please contact me any time ! THANK YOU ! ABKGroup research is supported by U.S. National Science Foundation, U.S. DARPA, Samsung, Qualcomm, NXP Semiconductors, Mentor Graphics, and the C-DEN Center. abk@ucsd.edu A. B. Kahng, 200813 CadenceLive academic track