Memories in SystemVerilog: ROM, RAM, and Descriptions

COMP541 Specifying Memories in SystemVerilog Montek Singh

Overview of ROM and RAM 2

Read-Only Memory (ROM) Memory that is permanent often the data is baked into during fabrication there are ROM flavors that allow updates PROM, EEPROM, etc. updates are typically infrequent or sporadic Top-level view: k address lines 2k data locations n bits of data at each location 3

Read-Write Memory (RAM) Allows reads and writes with similar speeds called random-access memory (RAM) as opposed to spools of tape sequential access Top-level view: k address lines 2k data locations n bits of data/location data input as well Need a line to specify reading or writing typically only one wire needed sometimes two separate ones 4

SystemVerilog Behavioral descriptions of: ROM, single-ported RAM, dual-ported RAM, etc. 5

SystemVerilog: 1-port RAM RAM example single-ported one address (for reading and writing) whether read or written is determined by write enable clock all writes take place on clock tick reads are asynchronous i.e., output after a propagation delay without waiting for a clock tick addr 1-port RAM dout din wr clock 6

SystemVerilog: 1-port RAM The actual storage where data resides logic [Dbits-1:0] mem [Nloc-1:0]; always_ff @(posedge clock) if(wr) mem[addr] <= din; Write operation on clock tick if write enabled Reading is asynchronous, no clock involved assign dout = mem[addr]; addr 1-port RAM dout din wr clock 7

SystemVerilog: 2-port RAM RAM example 2 ports one read-write port (using addr1) one read-only port (using addr2) 2 outputs: dout1 and dout2 only one data input: din dout1 dout2 read-write: addr1 read-only: addr2 2-port RAM din wr clock 8

SystemVerilog: 2-port RAM The actual storage where data resides logic [Dbits-1:0] mem [Nloc-1:0]; always_ff @(posedge clock) if(wr) mem[addr1] <= din; Write operation on clock tick if write enabled Reading is asynchronous, no clock involved assign dout1 = mem[addr1]; assign dout2 = mem[addr2]; dout1 dout2 read-write: addr1 read-only: addr2 2-port RAM din wr clock 9

SystemVerilog: MIPS register file Register file 3 ports two read-only ports (using ReadAddr1 and ReadAddr2) one write-only port (using WriteAddr) 2 outputs: ReadData1 and ReadData2 one data input: WriteData special case: reading $0 always returns 0 ReadData1 ReadData2 ReadAddr1 ReadAddr2 WriteAddr 3-port register file WriteData wr clock 10

SystemVerilog: MIPS register file The actual storage where data resides logic [Dbits-1:0] rf [Nloc-1:0]; always_ff @(posedge clock) if(wr) rf[ ] <= ; Write operation on clock tick if write enabled Reading is asynchronous, no clock involved assign ReadData1= ? rf[ ]; assign ReadData2= ? rf[ ]; Reading $0 must always return 0 ReadData1 ReadData2 ReadAddr1 ReadAddr2 WriteAddr 3-port register file WriteData Skeleton only. You fill in the details (Lab 7). wr clock 11

SystemVerilog: memory initialization Specify a file that contains initial values one value per line: hex or binary use $readmemh for hex use $readmemb for binary logic [Dbits-1:0] mem[Nloc-1:0]; initial $readmemh( mem_data.mem , mem, 0, Nloc-1); always_ff @(posedge clock) assign Specifies the file that contains initial values 12

SystemVerilog: ROM example ROM example single-ported read-only, no writing no clock needed reads are asynchronous i.e., output appears after a propagation delay without waiting for a clock tick logic [Dbits-1:0] mem [Nloc-1:0]; initial $readmemh( mem_data.mem , mem, 0, Nloc-1); Read operation only, no writes assign dout = mem[addr]; 13

Summary Today we looked at: ROM vs. RAM SystemVerilog templates for memories 14