Memory and Debugging Techniques in Digital Circuit Design

Design, Memory, and Debugging CS 3220 Fall 2014 A C Hadi Esmaeilzadeh hadi@cc.gatech.edu Georgia Institute of Technology T Some slides adopted from Prof. Milos Prvulovic Alternative,Computing,Technologies

Base-10 Counting Example module Class(KEY,HEX0,HEX1); input [0:0] KEY; output [6:0] HEX0, HEX1; wire clock = ! KEY[0]; reg [3:0] cnthi, cntlo; always @(posedge clock) begin if(cntlo == 4'd9) begin cntlo <= 4'd0; if(cnthi == 4 d9) cnthi <= 4 d0; else cnthi <= cnthi + 4'd1; end else begin cntlo <= cntlo + 4'd1; end end SevenSeg dlo(HEX0,cntlo); SevenSeg dhi(HEX1,cnthi); endmodule module SevenSeg(sseg,num); output [6:0] sseg; input [1:0] num; assign sseg = (num == 2'd0) ? 7'b1000000 : (num == 2'd1) ? 7'b1111001 : (num == 2'd2) ? 7'b0100100 : endmodule 21 Jan 2014 Lecture 4: Clocks and PLLs 2

Debugging our circuits We can use LED Debugging A close cousin to printf debugging Use a LED to show the signal of interest, e.g. assign LEDG[0] = mysignal; Then clock the circuit really slowly (e.g. using a KEY) Problems with LED Debugging Very tedious, takes a lot of time to get to the cycle you want (e.g. if the problem is in the 500th cycle) The key you use for clocking will wear out eventually 23 Jan 2014 Lecture 4: Clocks and PLLs 3

Debugging Demo We will use SignalTap Creates a little oscilloscope for your design and compiles it together with your design SignalTap stuff can be expensive (lots of memory bits and LEs) Can make design slower, too So remove SignalTap when bugs are fixed! Our demo design has 38LEs, 10Regs, 16K mem bits w/o SignalTap Tools-> SignalTap II Logic Analyzer First set your clock signal as the clock for SignalTap Set Sample Depth to # of cycles you want to record Right-click the Instance and Enable Power-Up Trigger Add wires/regs you want to record Recompile design, program board, then in SignalTap do Read Data 23 Jan 2014 Lecture 4: Clocks and PLLs 4

Debouncing If it s used as an edges-are-important signal, it needs a debouncing circuit: Change output (debounced signal) only if input (SW signal) is stable for multiple clock periods. This involves a counter, etc. Why does KEY work just fine? Because it is already debounced! Board has a special circuit to filter and condition KEY signals, but no such circuit on SW 23 Jan 2014 Lecture 4: Clocks and PLLs 5

Using SW Bouncing Effects Try counting how many times SW[0] went 0->1 Doesn t always work as expected When we move the switch from 0 to 1 position, sometimes the count increment is >1 When we move the switch from 1 to 0 position, sometimes the count changes! What s going on? Bouncing! 1. As contacts get close, vibration causes multiple touches before they are firmly together (or apart) 2. Sudden change in current causes voltage to bounce 23 Jan 2014 Lecture 4: Clocks and PLLs 6

Lets see if you remember If the highest clock frequency is 100MHz for this: reg [15:0] cnt; always @(posedge clock) cnt <= cnt + 16'd1; What is the highest clock frequency for this: reg [15:0] upcnt,dncnt; always @(posedge clock) begin upcnt <= upcnt + 16'd1; dncnt <= dncnt - 16'd1; end 21 Jan 2014 Lecture 4: Clocks and PLLs 7

Lets see if you remember If the highest clock frequency is 100MHz for this: reg [15:0] cnt; always @(posedge clock) cnt <= cnt + 16'd1; What is the highest clock frequency for this: reg [15:0] upcnt,dncnt; always @(posedge clock) begin upcnt <= upcnt + 16'd1; dncnt <= dncnt - 16'd1; end 21 Jan 2014 Lecture 4: Clocks and PLLs 8

Repetition in multi-bit signals Example: sign-extender again module SXT(IN,OUT); parameter IBITS; parameter OBITS; input [(IBITS-1):0] IN; output [(OBITS-1):0] OUT; assign OUT={{(OBITS-IBITS){IN[IBITS-1]}},IN};; endmodule SXT #(.IBITS(4),.OBITS(8)) sxt1(SW[3:0],LEDG); 21 Jan 2014 Lecture 4: Clocks and PLLs 9

Using = vs. <= Two types of state assignment in Verilog = is called a blocking assignment <= is called a non-blocking assignment We only used <= until now Computes RHS expression during the cycle Latches value into LHS at end of cycle (e.g. posedge) All <= happen simultaneously (at clock edge) Multiple <= to the same reg? Same @always block? Last one wins! Different @always blocks? Conflict (can t synthesize)! 21 Jan 2014 Lecture 4: Clocks and PLLs 10

What about = Two big differences Changes value of LHS as soon as RHS computed Delays subsequent = until the current one is done What does this do? always @(posedge clock) begin stage1 <= stage2 + 1; stage2 <= stage1; end What does this do? always @(posedge clock) begin stage1 = stage2 + 1; stage2 = stage1; end 21 Jan 2014 Lecture 4: Clocks and PLLs 11

Using always for combinatorial logic module ALU(A,B,CTL,OUT); parameter BITS; parameter CBITS; parameter CMD_ADD=0, CMD_SUB=1, CMD_LT=2, CMD_LE=3, CMD_AND=4, CMD_OR=5, CMD_XOR=6, CMD_NAND=7, CMD_NOR=8, CMD_NXOR=9; input [(CBITS-1):0] CTL; input [(BITS-1):0] A,B; output [(BITS-1):0] OUT; reg [(BITS-1):0] tmpout; CMD_LT: tmpout = (A<B); CMD_LE: tmpout = (A<=B); CMD_AND: tmpout = A&B; CMD_OR: tmpout = A|B; CMD_XOR: tmpout = A^B; CMD_NAND: tmpout = ~(A&B); CMD_NOR: tmpout = ~(A|B); CMD_NXOR: tmpout = ~(A^B); default: tmpout = Something; endcase end assign OUT=tmpout; endmodule tmpout is optimized out! But only if new value fully defined always @(A or B or CTL) begin case(CTL) CMD_ADD: tmpout = A+B; CMD_SUB: tmpout = A-B; 21 Jan 2014 Lecture 4: Clocks and PLLs 12

Using always for combinatorial logic module ALU(A,B,CTL,OUT); parameter BITS; parameter CBITS; parameter CMD_ADD=0, CMD_SUB=1, CMD_LT=2, CMD_LE=3, CMD_AND=4, CMD_OR=5, CMD_XOR=6, CMD_NAND=7, CMD_NOR=8, CMD_NXOR=9; input [(CBITS-1):0] CTL; input [(BITS-1):0] A,B; output [(BITS-1):0] OUT; reg [(BITS-1):0] tmpout; CMD_LT: tmpout = (A<B); CMD_LE: tmpout = (A<=B); CMD_AND: tmpout = A&B; CMD_OR: tmpout = A|B; CMD_XOR: tmpout = A^B; CMD_NAND: tmpout = ~(A&B); CMD_NOR: tmpout = ~(A|B); CMD_NXOR: tmpout = ~(A^B); default: tmpout = {BITS{1'bX}}; endcase end assign OUT=tmpout; endmodule always @(A or B or CTL) begin case(CTL) CMD_ADD: tmpout = A+B; CMD_SUB: tmpout = A-B; What is X here? 21 Jan 2014 Lecture 4: Clocks and PLLs 13

Is FFFF<1 ? module ALU(A,B,CTL,OUT); parameter BITS; parameter CBITS; parameter CMD_ADD=0, CMD_SUB=1, CMD_LT=2, CMD_LE=3, CMD_AND=4, CMD_OR=5, CMD_XOR=6, CMD_NAND=7, CMD_NOR=8, CMD_NXOR=9; input [(CBITS-1):0] CTL; input [(BITS-1):0] A,B; output [(BITS-1):0] OUT; wire signed [(BITS-1):0] A,B; reg signed [(BITS-1):0] tmpout; CMD_LT: tmpout = (A<B); CMD_LE: tmpout = (A<=B); CMD_AND: tmpout = A&B; CMD_OR: tmpout = A|B; CMD_XOR: tmpout = A^B; CMD_NAND: tmpout = ~(A&B); CMD_NOR: tmpout = ~(A|B); CMD_NXOR: tmpout = ~(A^B); default: tmpout = {CBITS{1'bX}}; endcase end assign OUT=tmpout; endmodule CMD_ADD: tmpout = A+B; CMD_SUB: tmpout = A-B; always @(A or B or CTL) begin case(CTL) 21 Jan 2014 Lecture 4: Clocks and PLLs 14

For loops Example: sign-extender module module SXT(IN,OUT); parameter IBITS; parameter OBITS; input [(IBITS-1):0] IN; output [(OBITS-1):0] OUT; reg [(OBITS-1):0] tmpout; integer i; always @(IN) begin tmpout[(IBITS-1):0]=IN; for(i=IBITS;i<OBITS;i=i+1) begin tmpout[i]=IN[IBITS-1]; end end assign OUT=tmpout; endmodule // This is how you can use this module: SXT #(.IBITS(4),.OBITS(8)) sxt1(SW[3:0],LEDG); 21 Jan 2014 Lecture 4: Clocks and PLLs 15

Parametrized modules Example: code similar for 2-bit, 4-bit, etc. counter Want to write one module for all of these module counter(IN,OUT); parameter BITS,INC; input IN; output [(BITS-1):0] OUT; reg [(BITS-1):0] state; always @(posedge IN) state<=state+INC; assign OUT=state; endmodule counter #(4,1) cnt1(clock,count); counter #(.INC(3),.BITS(8)) cnt2(clock,count); 21 Jan 2014 Lecture 4: Clocks and PLLs 16

Lets see if you remember If the highest clock frequency is 100MHz for this: reg [15:0] cnt; always @(posedge clock) cnt <= cnt + 16'd1; What is the highest clock frequency for this: reg [15:0] upcnt,dncnt; always @(posedge clock) begin upcnt <= upcnt + 16'd1; dncnt <= dncnt - 16'd1; end 21 Jan 2014 Lecture 4: Clocks and PLLs 17

If-then-else within always always @(posedge clock) begin if(cnt == 2'd2) cnt <= 2'd0; else cnt <= cnt + 2'd1; end MUX What does if-then-else translate into? 21 Jan 2014 Lecture 4: Clocks and PLLs 18

Memories in Verilog What does this do? reg [15:0] mem; It creates a 16-bit register (FF), mem[0] is LSB What is a memory? Conceptually, it s a bunch of registers We use an address to choose which one to access In Verilog, we describe a memory like this: reg [15:0] mem[0:1023]; This mem has 1024 words, each with 16 bits 23 Jan 2014 Lecture 4: Clocks and PLLs 19

Putting data in a memory File -> New, then Memory Initialization File Now we specify the format of the memory And can edit the memory content Or write a program to generate this content (Assign2) Then tell Verilog to use this to initialize our mem reg [15:0] mem[0:1023]; (* ram_init_file = SomeFile.mif" *) Each memory object can have one of these E.g. if there is separate inst memory and data memory we can have different .mif files to initialize them 23 Jan 2014 Lecture 4: Clocks and PLLs 20

Example! (* ram_init_file = "Mem.mif" *) reg [15:0] mem[0:1023]; // 1024-entry, 16-bit memory reg [15:0] mdr; // 16-bit MDR register reg [9:0] mar; // 10-bit MAR register initial mar = 10'd0; // MAR starts with value zero always @(posedge clock) begin mdr <= mem[mar]; // Read memory mar <= mar + 10 d1; // And increment mar register end // Do something with MDR, e.g. display it: SevenSeg sseg0(.IN(mdr[ 3: 0]),.OUT(HEX0)); SevenSeg sseg1(.IN(mdr[ 7: 4]),.OUT(HEX1)); SevenSeg sseg2(.IN(mdr[11: 8]),.OUT(HEX2)); SevenSeg sseg3(.IN(mdr[15:12]),.OUT(HEX3)); 23 Jan 2014 Lecture 4: Clocks and PLLs 21

Lets try without the MDR! always @(posedge clock) begin mar <= mar + 10 d1; // Increment mar register end // Do something with MDR, e.g. display it: SevenSeg sseg0(.IN(mem[mar][ 3: 0]),.OUT(HEX0)); SevenSeg sseg1(.IN(mem[mar][ 7: 4]),.OUT(HEX1)); SevenSeg sseg2(.IN(mem[mar][11: 8]),.OUT(HEX2)); SevenSeg sseg3(.IN(mem[mar][15:12]),.OUT(HEX3)); Compiles (not syntax error). But doesn t work! 23 Jan 2014 Lecture 4: Clocks and PLLs 22

This works but our memory is optimized out! always @(posedge clock) begin mar <= mar + 10 d1; // Increment mar register end wire [15:0] memout=mem[mar]; // Do something with MDR, e.g. display it: SevenSeg sseg0(.IN(memout[ 3: 0]),.OUT(HEX0)); SevenSeg sseg1(.IN(memout[ 7: 4]),.OUT(HEX1)); SevenSeg sseg2(.IN(memout[11: 8]),.OUT(HEX2)); SevenSeg sseg3(.IN(memout[15:12]),.OUT(HEX3)); 23 Jan 2014 Lecture 4: Clocks and PLLs 23

Getting memory to behave This (almost) always works as expected Memory address for reading comes from a FF (reg) Value read from memory only latched into FF (reg) No logic that sees the value directly (Almost) everything else can misbehave Unless you know exactly what you are doing Sometimes you still get surprised Why? Will come back to this eventually For now, just read memory using FFs 23 Jan 2014 Lecture 4: Clocks and PLLs 24

Debugging our circuits We can use LED Debugging A close cousin to printf debugging Use a LED to show the signal of interest, e.g. assign LEDG[0] = mysignal; Then clock the circuit really slowly (e.g. using a KEY) Problems with LED Debugging Very tedious, takes a lot of time to get to the cycle you want (e.g. if the problem is in the 500th cycle) The key you use for clocking will wear out eventually 23 Jan 2014 Lecture 4: Clocks and PLLs 25

Debugging Demo We will use SignalTap Creates a little oscilloscope for your design and compiles it together with your design SignalTap stuff can be expensive (lots of memory bits and LEs) Can make design slower, too So remove SignalTap when bugs are fixed! Our demo design has 38LEs, 10Regs, 16K mem bits w/o SignalTap Tools-> SignalTap II Logic Analyzer First set your clock signal as the clock for SignalTap Set Sample Depth to # of cycles you want to record Right-click the Instance and Enable Power-Up Trigger Add wires/regs you want to record Recompile design, program board, then in SignalTap do Read Data 23 Jan 2014 Lecture 4: Clocks and PLLs 26

Using SW Bouncing Effects Try counting how many times SW[0] went 0->1 Doesn t always work as expected When we move the switch from 0 to 1 position, sometimes the count increment is >1 When we move the switch from 1 to 0 position, sometimes the count changes! What s going on? Bouncing! 1. As contacts get close, vibration causes multiple touches before they are firmly together (or apart) 2. Sudden change in current causes voltage to bounce 23 Jan 2014 Lecture 4: Clocks and PLLs 27

Debouncing If it s used as an edges-are-important signal, it needs a debouncing circuit: Change output (debounced signal) only if input (SW signal) is stable for multiple clock periods. This involves a counter, etc. Why does KEY work just fine? Because it is already debounced! Board has a special circuit to filter and condition KEY signals, but no such circuit on SW 23 Jan 2014 Lecture 4: Clocks and PLLs 28

Key presses But how do we do clear, stopped, running? reg clear=1 b1,running=1 b0,stopped=1 b0; always @(negedge KEY[0]) {clear ,running,stopped}<= {stopped,clear ,running}; Nooooo! This is NOT a synchronous design! How about always @(posedge clk) if(!KEY[0]) {clear ,running,stopped}<= {stopped,clear ,running}; Now it s synchronous but incorrect 16 Jan 2014 Project 1 Tips and Tricks 29

Key presses reg [3:0] oldKEY=4'b1111; always @(posedge clk) oldKEY<=KEY; wire KEY0Pushed= {oldKEY[0],KEY[0]}==2'b10; Now we can do always @(posedge clk) if(KEY0Pushed) {clear ,running,stopped}<= {stopped,clear ,running}; 16 Jan 2014 Project 1 Tips and Tricks 30

How do we choose the frequency? Using timing analysis results! Compile design, look at Compilation Report Under TimeQuest Timing Analyzer , Click on Slow Model , then Fmax Summary It tells you the max frequency for your design Fmax higher than your PLL s frequency Increase the PLL frequency (faster processor) Fmax lower than your PLL s frequency? There will be a critical warning Don t submit projects that have this warning! Design will be graded as incorrect! Even if it works! 16 Jan 2014 Lecture 4: Clocks and PLLs 31

The rest of it Lap-time functionality (KEY[1]) Another set of regs to hold lap time Display selects between time and lap time How do we select? Get rid of the / and % for seconds How? 16 Jan 2014 Project 1 Tips and Tricks 32