Memory Hierarchy and Cache Designs
Explore the intricate design aspects of memory hierarchy and cache systems, including types of caches, mapping strategies, and crucial considerations in cache design. Delve into fundamental concepts in computer organization and design for optimal system performance.
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Presentation Transcript
Model of Memory Hierarchy Increasing Speed Physical Memory Virtual Memory SRAM DRAM DISK Main Memory Reg File L1 Data cache L2 Cache L1 Inst cache Increasing Capacity 2
3 Four Central Questions in Designing a Cache P-I-R-W: placement: where can a block of memory go? identification: how do i find a block of memory? replacement: how do i make space for new blocks? write policy: how do i propagate changes? need to consider these for all levels of the memory hierarchy L1/L2/L3 caches now main memory, disks have similar issues, addressed later ECE 411 COMPUTER ORGANIZATION AND DESIGN
4 Types of Caches type of cache direct mapped (DM) mapping of data from memory to cache a memory value can be placed at a single corresponding location in the cache a memory value can be placed in any of a set of locations in the cache complexity of searching the cache fast indexing mechanism set- associative (SA) slightly more involved search mechanism fully- associative (FA) a memory value can be placed in any location in the cache extensive hardware resources required to search (CAM) ECE 411 COMPUTER ORGANIZATION AND DESIGN
Direct Mapping Direct mapping: A memory value can only be placed at a single corresponding location in the cache Index Tag Data 0 00000 00000 0 0x55 0x55 0x0F 0x0F 1 00000 00000 00000 1 00001 0 11111 11111 0 0xAA 0xAA 0xF0 0xF0 11111 11111 11111 1 5
Direct-Mapped: One cache location for each address Address Tag Set Offset Cache Set field selects line in cache Tag Data Compare Requested Data Hit 4/19/2025 6
Fully Associative Mapping Fully-associative mapping: A memory value can be placed anywhere in the cache Tag Data 0000 000000 0000 000000 0x55 0x55 0x55 0x55 0x0F 0x0F 0x0F 0x0F 0000 000001 0000 000001 000110 000110 1111 111110 1111 111110 0xAA 0xAA 0xAA 0xAA 0xF0 0xF0 0xF0 0xF0 1111 111111 1111 111111 7
Fully-Associative: Anything Can Go Anywhere Address Tag Offset Check each line in parallel Cache Compare Compare Compare Compare Compare Compare Compare Compare Select line to return based on which line hit Requested Data 4/19/2025 8
Set Associative Mapping (2-Way) Set-associative mapping: A memory value can be placed in any location of a set in the cache Index Data Tag Way 0 Way 1 0 0000 0 0000 0 0x55 0x55 0 0x0F 0x0F 1 0000 1 0000 1 1 0 1111 0 1111 0 0 0xAA 0xAA 0xF0 0xF0 1111 1 1111 1 1 9
Compromise: Set-Associative Caches Address Tag Set Offset Select Set In Cache Way Set Cache Check all ways of a set in parallel Compare Compare Hit? Hit? Requested Data 4/19/2025 10
Write-through Policy 0x1234 0x1234 0x1234 0x5678 0x5678 0x1234 Processor Cache Memory 11
Write-back Policy 0x1234 0x1234 0x1234 ????? 0x5678 0x9ABC 0x1234 0x5678 0x5678 Processor Cache Memory Write miss 12
