Mitigating Wordline Crosstalk using Adaptive Trees of Counters
Explore the innovative approach of mitigating wordline crosstalk in DRAM using dynamically reconfigured counter-based adaptive trees. Learn about the challenges of DRAM scaling, voltage fluctuations, and the impact of crosstalk on memory capacity. Discover solutions such as probabilistic and deterministic techniques like CAT and DRCAT for efficient counter assignment and row activation. Dive into related works and explore the probabilistic row activation method for refreshing victim rows. Uncover the dynamic challenges in DRAM cells and how adaptive trees of counters provide effective mitigation strategies.
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Mitigating Wordline Crosstalk using Adaptive Trees of Counters Mohammad Seyedzadeh, Alex Jones, Rami Melhem University of Pittsburgh
Wordline Crosstalk in DRAM DRAM Scaling High Memory Capacity Voltage Fluctuations DRAM Cells Deep-scaled DRAM Cells 2 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Wordline Crosstalk in DRAM Row of Cells Row of Cells Victim Row Wordline Aggressor Row Victim Row DRAM Bank DRAM Cells Deep-scaled DRAM Cells The malicious exploit of this crosstalk by repeatedly accessing a row to induce this effect is known as row hammering. 2 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Outline Wordline Crosstalk in DRAM Probabilistic and Deterministic Solutions CAT: Counter based Adaptive Tree Evaluation Conclusion 3 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Wordline Crosstalk in DRAM: Related Work Probabilistic Approach Deterministic Approach Deep-scaled DRAM Cells Probabilistic Row Activation (PRA) Static Counter Assignment (SCA) 4 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Probabilistic Row Activation (PRA) Probabilistic Approach RNG(p) Deep-scaled DRAM Cells Using a Random Number Generator to refresh the victim rows with the probability of p . 5 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Probabilistic Row Activation (PRA) Refresh? Threshold? (T)? 32k? 24k? 16k? 8k? PRA Failure Probability 1.E+00? PRA? Unsurvivability? 1.E-04? ? for? 5? Years? 1.E-08? for 5 years 1.E-12? 1.E-16? 1.E-20? 1.E-24? 1.E-28? p=0.001? p=0.002? p=0.003? p=0.004? p=0.005? p=0.006? Chipkill? Pseudo Random Number Generator (PRNG) LFSR-based RNG Refresh threshold: # of aggressor row accesses before read disturbance errors occur in victim rows. 6 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Static Counter Assignment (SCA) C0 C0 ...... ... Cm ... Cn CN-1 Deep-scaled DRAM Cells Deep-scaled DRAM Cells 7 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Static Counter Assignment (SCA) Counters? (Sta c+Dynamic)? Counters? (Sta c+Dynamic)? Counters? (Sta c+Dynamic)? Refresh? Refresh? Refresh? Total? (refresh+counter? energy)? Total? (refresh+counter? energy)? Total? (refresh+counter? energy)? 1.E+07? 1.E+07? 1.E+07? 1.E+06? 1.E+06? 1.E+06? Energy? (nJ)? Energy? (nJ)? Energy? (nJ)? 1.E+05? 1.E+05? 1.E+05? Unutilized Counters 1.E+04? 1.E+04? 1.E+04? 1.E+03? 1.E+03? 1.E+03? 1.E+02? 1.E+02? 1.E+02? 1.E+01? 1.E+01? 1.E+01? 1.E+00? 1.E+00? 1.E+00? 16? 16? 16? 32? 32? 32? 64? 64? 64? 128? 128? 128? 256? 256? 256? 512? 512? 512? 1024? 1024? 1024? 2048? 2048? 2048? 8192? 8192? 8192? 16384? 16384? 16384? 32768? 32768? 32768? 65536? 65536? 65536? 4096? 4096? 4096? #? of? Counters? #? of? Counters? #? of? Counters? Non-uniform row access patterns in DRAM banks because of data locality 8 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
How to Efficiently Leverage Counters in the Crosstalk Mitigation? 8 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Our Solution: Counter-based Adaptive Tree (CAT) Row Address Active Counter Expired Counter DRAM BANK (N rows) 9 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Our Solution: Counter-based Adaptive Tree (CAT) Row Address Active Counter Expired Counter DRAM BANK (N rows) 10 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
CAT: Counter based Adaptive Tree PRCAT: Periodically Reset CAT Burst Refresh Mechanism Reset CAT at the end of each refresh Interval DRCAT: Dynamically Reconfigured CAT Distributed Refresh Mechanism Reconfigure CAT during consecutive refresh intervals 11 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
PRCAT: Periodically Reset CAT C0 Burst Refresh 64ms 64ms 12 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
PRCAT: Periodically Reset CAT I0 C0 C1 C0 Burst Refresh 64ms 64ms 12 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
PRCAT: Periodically Reset CAT I0 C1 I1 C0 I2 I3 I4 C3 C6 C1 I5 C4 C2 C5 Burst Refresh 64ms 64ms 12 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
PRCAT: Periodically Reset CAT C0 I0 I1 C0 I2 I3 I6 C6 I4 C3 C1 C6 C7 I5 C4 C2 C5 Reset CAT Build CAT from the Root Burst Refresh 64ms 64ms 12 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
DRCAT: Dynamically Reconfigured CAT I0 I1 C0 I2 I3 I4 C3 I6 C1 C6 C6 C7 I5 C4 C2 C2 C5 C5 Distributed Refresh 64ms 64ms 13 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
DRCAT: Dynamically Reconfigured CAT ? ? W? C? ? I? I0 I0 ? ? ? ? ? ? ?? ? ? ? I1 C0 I0? I1? C0? 1? I1? I2? I3? I2?C1? I4? I3?C3? I6? I4?C5? I5?C6? I6? I5? ? 0? ?C0? ? 0? 1? ?C1? ? 0? 1? ?C2? ? 1? 1? ?C3? ? 1? 0? ?C4? ? 0? 0? ?C5? ? 0? 0? ?C6? ? 1? I1 C0 1? 0? 0? I2 I3 I2 I3 M-1? ? I4 I6 C1 C3 M? ? I4 C3 I6 C1 C4? 0? C2? C7? 1? I5 C4 C7 0? C5 I5 C6 C7 I5 C4 C2 C6 C2 C2 C5 L-ptr? R-ptr? L-leaf? R-leaf??C7? ? 1? (a)? (b)? (c)? (d)? Distributed Refresh During each row access, the tree structure is traversed sequentially by chasing the pointers to find the counter assigned to a specific row address. 64ms 64ms 13 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Experimental Settings USIMM Simulator: Two 3.2GHz cores, 2 channels(each 8GB DIMM), 1 rank/channel 8 banks/rank, 64K rows/bank Synopsys Design Compiler Power Overhead Performance Overhead PARSEC, SPEC, Commercial and Biobench Kernel Malicious Attack 14 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Power Overhead 30% Probabilistic Row Activation Static Counter Assignment 25% PRCAT DRCAT 20% 15% 10% 5% 0% com1 com2 com3 com4 com5 swapt fluid str black ferret face freq MTC MTF libq leslie mum tigr Mean COMM PARSEC SPEC BIO Power overhead for DRCAT in dual-core systems is 4.5%, which is an improvement over the 12% and 13% incurred in PRA and SCA. 15 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Performance Overhead 4% Probabilistic Row Activation Static Counter Assignment 3% PRCAT DRCAT 2% 1% 0% com1 com2 com3 com4 com5 swapt fluid str black ferret face freq MTC MTF libq leslie mum tigr Mean COMM PARSEC SPEC BIO DRCAT, PRCAT and PRA incur very low performance overhead (<0.5%). 16 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Sensitivity Analysis 25% Power Overhead Mapping Policy & Number of Cores 20% 15% DRCAT reduces the power overhead in quad-core systems to 7%, which is an improvement over the 21% and 18% incurred in SCA and PRA. 10% 5% 0% SCA_128 SCA_256 SCA_256 DRCAT_64 PRCAT_128 PRCAT_128 PRA_0.003 PRA_0.003 PRA_0.003 DRCAT_128 DRCAT_128 PRCAT_64 dual-core/2channels quad-core/2channels quad-core/4channels 15% Power Overhead Refresh Thresholds 10% Scaling down DRAM technology exacerbates the crosstalk problem leading to a decrease in the refresh threshold. 5% 0% DRCAT_1 PRCAT_1 SCA_128 SCA_128 SCA_128 DRCAT_32 DRCAT_64 DRCAT_64 SCA_256 PRA_0.001 PRA_0.002 PRA_0.003 PRA_0.005 PRCAT_32 PRCAT_64 PRCAT_64 17 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Performance Overhead under Malicious attacks 5% 4% 3% 2% 1% <0.9% 0% DRCBT_128 DRCBT_128 DRCBT_128 SCA_128 PRCBT_64 SCA_128 PRCBT_64 SCA_128 PRCBT_64 SCA_128 PRCBT_64 SCA_128 PRCBT_64 SCA_128 PRCBT_64 SCA_256 SCA_256 SCA_256 DRCBT_64 DRCBT_64 DRCBT_64 DRCBT_64 DRCBT_64 DRCBT_64 PRCBT_128 PRCBT_128 PRCBT_128 Heavy Medium Light Heavy Medium Light Heavy Medium Light T=32K T=16K T=8K As expected, more intensive attacks leads to higher ETO since it causes more refreshes. 18 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Conclusion Demonstrated that a small number of counters can be implemented on chip to mitigate wordline crosstalk. Proposed a non-uniform counter assignment, Counter-Based Adaptive Tree, to more precisely determine the aggressor rows. Introduced a scheme, DRCAT, for dynamically reconfiguring the CAT to track the temporal changes in memory access patterns . DRCAT avoids wordline crosstalk during normal execution and protects against malicious attacks. 19 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Thank you for your attention! Question? 20 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Hardware Overhead Hardware energy (per bank) and area of DRCAT, PRCAT and SCA for different number of counters The specification of the PRNG used for PRA. The reported energy for PRNG (eng_PRNG) is for generating 9-bits per row access. Area (mm2) Energy: dynamic (nJ per row access) and static (nJ per refresh interval) DRCAT PRCAT SCA M PRNG DRCAT PRCAT SCA dynamic static dynamic static dynamic static 32 3.05E-04 5.77E+03 2.91E-04 5.55E+03 1.41E-04 3.16E+03 3.16E-02 3.04E-02 1.86E-02 Area 4.0E-3 64 4.30E-04 1.39E+04 4.09-04 1.32E+04 1.92E-04 8.81E+03 6.12E-02 5.86E-02 4.04E-02 Throughput(Gbps) 2.4 128 5.83E-04 2.77E+04 5.50E-04 2.63E+04 2.22E-04 1.44E+04 1.16E-01 1.11E-01 6.04E-02 Power(mW) 7 256 8.72E-04 5.44E+04 8.25E-04 5.13E+04 3.12E-04 2.39E+04 2.23E-01 2.11E-01 1.00E-01 Eff.(nj/b) 2.9E-3 512 1.17E-03 1.06E+05 1.10E-03 1.02E+05 4.25E-04 4.52E+04 3.93E-01 3.75E-01 1.72E-01 Eng_PRNG(nj) 2.62E-2 21 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Static Counter Assignment (SCA) Counters? (Sta: c+Dynamic)? 2KB? counter? cache? Refresh? 8KB? counter? cache? Total? (refresh+counter? energy)? 1.E+07? 1.E+06? Energy? (nJ)? 1.E+05? 1.E+04? 1.E+03? 1.E+02? 1.E+01? 1.E+00? 16? 32? 64? 128? 256? 512? 1024? 2048? 8192? 16384? 32768? 65536? 4096? #? of? Counters? 22 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
Sensitivity to the Maximum CAT depth 40%? CMRPO? 30%? T=32K? 20%? 10%? 0%? DRCAT_L6? DRCAT_L7? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L7? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? SCA? SCA? SCA? SCA? SCA? 32? 64? 128? 256? 512? 40%? CMRPO? 30%? T=16K? 20%? 10%? 0%? DRCAT_L6? DRCAT_L7? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L7? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L8? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L9? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? DRCAT_L10? DRCAT_L11? DRCAT_L12? DRCAT_L13? DRCAT_L14? SCA? SCA? SCA? SCA? SCA? 32? 64? 128? 256? 512? Crosstalk mitigation power overhead per bank for DRCAT using from 32 to 512 counters and different maximum CAT levels (6 to 14). 23 DRCAT: Dynamically Reconfigured Counter based Adaptive Tree
